Abstract: A system is provided for terminating processes that are executing on a plurality of distributed computing nodes. The system comprises a batch queuing system configured to receive jobs from a user and to dispatch jobs to the distributed computing nodes. A process shutdown interface is included that is configured to receive task criteria for terminating processes corresponding to the task criteria on the distributed computing nodes. An automatic process shutdown module is in communication with the process shutdown interface. The automatic process shutdown module is configured to retrieve information based on the task criteria from the batch queuing system regarding the processing location of jobs submitted to the batch queuing system. The automatic process shutdown module is also configured to terminate the processes on the computing nodes for jobs that are identified using the information obtained from the batch queuing system.

Abstract: A method for identifying predictable data sharing locations includes generating a testcase thread of code, creating a list of data lines used by the generated testcase thread of code, and generating a list of predictable data sharing locations based on the data line list.

Abstract: A method for testing the correct behavior of an integrated circuit includes forming a list of potential data sharing locations, collecting memory access statistics of the potential data sharing locations, and forming subsequent test case threads to test specialized processing conditions of the integrated circuit based on the memory access statistics of the potential data sharing locations.

Abstract: Method and system for automatically backtracing through a testcase file. First the testcase file is accessed. Next, a start line identifier for specifying an instruction line in the testcase file at which to begin processing is received. The instruction line in the testcase file that is specified by the start line identifier is processed first. The previous instruction lines in the testcase file are then processed in a sequential fashion until the beginning of the testcase file is reached.

Abstract: A system for detecting/avoiding memory usage conflicts when generating and merging multi-threaded software test cases. Initially, a test case generator is given a unique segment of memory which it can use. A plurality of test cases are generated, one at a time, by the test case generator. When the first test case is generated, the memory segment used is noted. When each of the second through Nth test cases is generated, a memory segment of the same size as the first test case, but not overlapping that of the previously assigned test case(s), is assigned to each subsequent test case.

Abstract: A system is provided for terminating processes that are executing on a plurality of distributed computing nodes. The system comprises a batch queuing system configured to receive jobs from a user and to dispatch jobs to the distributed computing nodes. A process shutdown interface is included that is configured to receive task criteria for terminating processes corresponding to the task criteria on the distributed computing nodes. An automatic process shutdown module is in communication with the process shutdown interface. The automatic process shutdown module is configured to retrieve information based on the task criteria from the batch queuing system regarding the processing location of jobs submitted to the batch queuing system. The automatic process shutdown module is also configured to terminate the processes on the computing nodes for jobs that are identified using the information obtained from the batch queuing system.

Abstract: A system for indicating attempts by a computer program to free memory that is not currently allocated, as well as indicating allocated memory that is never freed. In a particular software program, the programmer includes code that prints a short debug message to a text file every time that a memory allocation or a free-memory operation takes place. After the program completes execution, the text file contains a list of messages indicating all occurrences of memory allocation or free-memory operations. An automated parsing function examines the text file and provides error indications when memory allocation or de-allocation errors are detected.

Abstract: A system for detecting/avoiding memory usage conflicts when generating and merging multi-threaded software test cases. Initially, a test case generator is given a unique segment of memory which it can use. A plurality of test cases are generated, one at a time, by the test case generator. When the first test case is generated, the memory segment used is noted. When each of the second through Nth test cases is generated, a memory segment of the same size as the first test case, but not overlapping that of the previously assigned test case(s), is assigned to each subsequent test case.

Abstract: A method of converting a testcase designed to execute on a first member of a processor family to a converted testcase for execution on a second member of a processor family provides particularly for conversion of Translation Lookaside Buffer usage. The method is operable on a computer. The method involves automatically comparing each TLB location used by the testcase to TLB locations available in the second member of the processor family, or, if the second member of the processor family is a multiprocessor circuit, a standard partition available in the second member of the processor family. If the testcase uses only TLB locations that are available in the second member of the processor family, indicating that the testcase is runable on the second member of the processor family. In particular embodiments, TLB locations used by the testcase are automatically reassigned to locations available in the TLB, or standard partition of the TLB, in the second member of the processor family.

Abstract: A method and apparatus for converting a testcase written for a first member of a processor family to run on a second member of a processor family. The first and second members of the processor family have cache memory used by the testcase. The method includes steps of reading the testcase into a digital computer and searching for, and tabulating, cache initialization commands of the testcase. Tabulated cache initializations are then sorted by cache line address and way number and displayed. This information is used to determine whether the testcase will fit on the second member without modification, and to assist in making modifications to the testcase.

Abstract: A system for preventing translation cache/translation register initialization conflicts in dual-threaded computer processor architecture test cases. When each test case is generated, the test case generator is given a number T representing the total number translation cache entries and translation register entries which it can use. A first test case thread and a second test case thread are generated to produce a number of translation register entries and the number of translation cache entries equal to a value of no greater than T/4. Each of the translation register entries for the first test case thread and for the second test case thread is then moved to mutually exclusive slots in a range from 0 through (T/2−1). Finally, the translation cache entries for the first test case thread are moved to mutually exclusive slots (T−1) through T/2.

Abstract: A method of converting a testcase designed to execute on a first member of a processor family to a converted testcase for execution on a second member of a processor family provides particularly for conversion of Translation Lookaside Buffer usage. The method is operable on a computer. The method involves automatically comparing each TLB location used by the testcase to TLB locations available in the second member of the processor family, or, if the second member of the processor family is a multiprocessor circuit, a standard partition available in the second member of the processor family. If the testcase uses only TLB locations that are available in the second member of the processor family, indicating that the testcase is runable on the second member of the processor family. In particular embodiments, TLB locations used by the testcase are automatically reassigned to locations available in the TLB, or standard partition of the TLB, in the second member of the processor family.