Abstract: Techniques, structures, and systems are disclosed for implementing an efficient design of computer hardware using a top-to-bottom approach. In one aspect, a method for designing a processor includes generating an initial architecture for a processor to execute algorithms, simulating execution of the algorithms by the initial architecture to determine a modification to the initial architecture, and creating a processor design based on the modification to the initial architecture. The described method for implementing a hardware design tool provides a push-button transition from high level specification for algorithms to hardware description language.

Abstract: Specialized hardware functions for high assurance processing are seldom integrated into commodity processors. Furthermore, as chips increase in complexity, trustworthy processing of sensitive information can become increasingly difficult to achieve due to extensive on-chip resource sharing and the lack of corresponding protection mechanisms. Embodiments in accordance with the invention allow for enhanced security of commodity integrated circuits, using minor modifications, in conjunction with a separate integrated circuit that can provide monitoring, access control, and other useful security functions. In one embodiment, a separate control plane, stacked using 3-D integration technology, allows for the function and economics of specialized security mechanisms, not available from a coprocessor alone, to be integrated with the underlying commodity computing hardware.

Abstract: Techniques, structures, and systems are disclosed for implementing an efficient design of computer hardware using a top-to-bottom approach. In one aspect, a method for designing a processor includes generating an initial architecture for a processor to execute algorithms, simulating execution of the algorithms by the initial architecture to determine a modification to the initial architecture, and creating a processor design based on the modification to the initial architecture. The described method for implementing a hardware design tool provides a push-button transition from high level specification for algorithms to hardware description language.