Patents by Inventor Ryan D. Lane

Ryan D. Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9263186
    Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Yue Li, Xiaoming Chen, Zhongping Bao, Charles D. Paynter, Xiaonan Zhang, Ryan D. Lane
  • Patent number: 9131634
    Abstract: A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package. The first radio frequency package includes radio frequency components. The radio frequency package on package (PoP) circuit also includes a second radio frequency package. The second radio frequency package includes radio frequency components. The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: September 8, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Aristotele Hadjichristos, Gurkanwal Singh Sahota, Steven C Ciccarelli, David J Wilding, Ryan D Lane, Christian Holenstein, Milind P Shah
  • Patent number: 9035421
    Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 19, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Young K. Song, Yunseo Park, Xiaonan Zhang, Ryan D. Lane, Babak Nejati, Aristotele Hadjichristos, Xiaoming Chen
  • Patent number: 8890143
    Abstract: A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: November 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Ryan D. Lane, Ruey Kae Zang
  • Publication number: 20140252544
    Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Yue Li, Xiaoming Chen, Zhongping Bao, Charles D. Paynter, Xiaonan Zhang, Ryan D. Lane
  • Publication number: 20140246753
    Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 4, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Young K. Song, Yunseo Park, Xiaonan Zhang, Ryan D. Lane, Babak Nejati, Aristotele Hadjichristos, Xiaoming Chen
  • Publication number: 20120068175
    Abstract: A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 22, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Ryan D. Lane, Ruey Kae Zang