Abstract: An apparatus is disclosed for comparing a first input signal with a second input signal and generating an output signal representative of that comparison in response to a system clock signal. The apparatus comprises a plurality of amplifying circuits. A first amplifying circuit generates a pair of first amplifier signals representative of the input signals applied to the apparatus. A second amplifying circuit receives the pair of first amplifier signals and generates a pair of second amplifier signals representative of the pair of first amplifier signals. A delay circuit receives the system clock signal and generates a delayed clock signal which follows the system clock signal by predetermined interval. A first switching circuit is operatively connected across the first amplifier outputs and responds to the system clock signal. A second switching circuit is operatively connected across the second amplifier outputs and is responsive to the delayed clock signal.

Abstract: There is disclosed a synchronizing circuit for synchronizing a first clock signal to a second clock signal. The synchronizing circuit includes an edge-triggered set-reset latch and a delay circuit. A subclock generator generates first and second subclock signals from a synchronizing clock to control the delay circuit so that the synchronized signal at the output of the circuit is exactly one full cycle period of the synchronizing clock signal.