Abstract: This document relates to power consumption of computing devices. One example is a face detection circuit that includes a camera interface, a processing component, and a power management interface. The camera interface can be configured to communicate with a camera. The processing component can be configured to instruct the camera to provide image data at multiple levels of resolution, and perform multiple stages of analysis on the image data obtained from the camera to detect the presence of a face in the image data. The power management interface can be configured to output an indication when the face is detected in the image data.

Abstract: Methods, apparatus, and computer-readable storage media are disclosed for applying filtering operations to data transferred as part of a direct memory access (DMA) operation. In one example of the disclosed technology, a system includes a processor, memory, and a direct memory access (DMA) engine coupled to the memory for reading a set of data from a selected range of read memory addresses for the memory without using the processor. A line buffer coupled to the DMA engine is configured to receive DMA read data and temporarily store a portion, but not all of the data set being read by the DMA engine in a line buffer. A digital filter is configured to apply a filtering operation to a windowed subset of the buffered portion of the data set, producing filtered data that is stored to a selected range of write memory addresses for the memory, without using the processor.

Abstract: Embodiments are disclosed for a method of executing instructions in a processing core of a microprocessor. In one embodiment, the method comprises, in a first clock domain, receiving an input from a second clock domain external to the first clock domain, the input comprising an indication from the second clock domain regarding whether to execute an instruction in the first clock domain. The method further comprises synchronizing the input from the second clock domain with the first clock domain, if the instruction is a predicatable instruction and the indication matches a predicate condition that indicates not to perform the instruction, then not performing the instruction, and otherwise performing the instruction.

Abstract: Apparatus and methods are disclosed for reordering data received in a non-contiguous order into a contiguous order. In one example of the disclosed technology, an apparatus includes a number of input buffers comprising at least a first, first-in first-out (FIFO) input buffer and a second FIFO input buffer, a number of FIFO output buffers, and a reorder unit configured to store a first portion of non-contiguous data received from an image sensor in the first input buffer, store a second portion of the received data in the second FIFO input buffer, store a respective pixel of data output by the first and second FIFO input buffers at a first address location in the memory, and traverse the memory according to an order to store the respective pixels in a FIFO output buffer. The apparatus can thus be used to reorder pixel data prior to further image processing.

Abstract: A digital signal processor includes a variable precision hardware pipeline that provides a maximum level of precision using a first plurality of bits for a mathematical representation. The pipeline stages include data registers to store the first plurality of bits. A precision select module selects a level of precision for processing a block of instructions and sets a precision control register. Logic circuitry utilizes the precision control register to gate the clock signal for one or more of the first plurality of bits to reduce the precision of the hardware pipeline. The logic circuitry disables the clock signal for the data latches in the pipeline corresponding to bits to be disabled to reduce the precision. By disabling the clock signal for the data registers, the amount of power consumed by the pipeline can be reduced.

Abstract: This document relates to power consumption of computing devices. One example is a face detection circuit that includes a camera interface, a processing component, and a power management interface. The camera interface can be configured to communicate with a camera. The processing component can be configured to instruct the camera to provide image data at multiple levels of resolution, and perform multiple stages of analysis on the image data obtained from the camera to detect the presence of a face in the image data. The power management interface can be configured to output an indication when the face is detected in the image data.

Abstract: Apparatus and methods are disclosed for reordering data received in a non-contiguous order into a contiguous order. In one example of the disclosed technology, an apparatus includes a number of input buffers comprising at least a first, first-in first-out (FIFO) input buffer and a second FIFO input buffer, a number of FIFO output buffers, and a reorder unit configured to store a first portion of non-contiguous data received from an image sensor in the first input buffer, store a second portion of the received data in the second FIFO input buffer, store a respective pixel of data output by the first and second FIFO input buffers at a first address location in the memory, and traverse the memory according to an order to store the respective pixels in a FIFO output buffer. The apparatus can thus be used to reorder pixel data prior to further image processing.

Abstract: Methods, apparatus, and computer-readable storage media are disclosed for applying filtering operations to data transferred as part of a direct memory access (DMA) operation. In one example of the disclosed technology, a system includes a processor, memory, and a direct memory access (DMA) engine coupled to the memory for reading a set of data from a selected range of read memory addresses for the memory without using the processor. A line buffer coupled to the DMA engine is configured to receive DMA read data and temporarily store a portion, but not all of the data set being read by the DMA engine in a line buffer. A digital filter is configured to apply a filtering operation to a windowed subset of the buffered portion of the data set, producing filtered data that is stored to a selected range of write memory addresses for the memory, without using the processor.

Abstract: Apparatus and methods are disclosed for performing mathematical operations that can be applied in a number of processor architectures. In one example of the disclosed technology, a lookup table is configured to return two or more function values based on an input operand of a single processor instruction storing a fixed-point number. A control unit is configured to execute the instruction by addressing the lookup table based on an index portion of the input operand, and an interpolation module is configured to interpolate an output value based on two or more of the returned function values by scaling at least one of the returned function values by a fractional portion of the input operand. In some examples, a second instruction can be used to store the function values in the lookup table.

Abstract: A digital signal processor includes a variable precision hardware pipeline that provides a maximum level of precision using a first plurality of bits for a mathematical representation. The pipeline stages include data registers to store the first plurality of bits. A precision select module selects a level of precision for processing a block of instructions and sets a precision control register. Logic circuitry utilizes the precision control register to gate the clock signal for one or more of the first plurality of bits to reduce the precision of the hardware pipeline. The logic circuitry disables the clock signal for the data latches in the pipeline corresponding to bits to be disabled to reduce the precision. By disabling the clock signal for the data registers, the amount of power consumed by the pipeline can be reduced.

Abstract: Embodiments are disclosed for a method of executing instructions in a processing core of a microprocessor. In one embodiment, the method comprises, in a first clock domain, receiving an input from a second clock domain external to the first clock domain, the input comprising an indication from the second clock domain regarding whether to execute an instruction in the first clock domain. The method further comprises synchronizing the input from the second clock domain with the first clock domain, if the instruction is a predicatable instruction and the indication matches a predicate condition that indicates not to perform the instruction, then not performing the instruction, and otherwise performing the instruction.

Abstract: Concurrent read access and exclusive write access are provided in a shared memory architecture to permit one or more devices in the shared memory architecture to maintain read access to a block of memory such as a cache line while one device has exclusive permission to modify that block of memory. By doing so, a device that has permission to modify may make updates to its copy of the block of memory without invalidating other copies of the block of memory, and potentially enabling other devices to continue to read data from their respective copies of the block of memory without having to retrieve the updated copy of the block of memory.

Abstract: An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system.