Patents by Inventor Ryan Huang

Ryan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132520
    Abstract: The invention provides compounds of formula (I): wherein the variables are defined in the specification, or a pharmaceutically-acceptable salt thereof, that are inhibitors of JAK kinases. The invention also provides pharmaceutical compositions comprising such compounds, methods of using such compounds to treat inflammatory bowel diseases, and processes and intermediates useful for preparing such compounds.
    Type: Application
    Filed: September 5, 2023
    Publication date: April 25, 2024
    Inventors: Ryan Hudson, Jennifer Kozak, Paul R. Fatheree, Dante D. Podesto, Gary E.L. Brandt, Melissa Fleury, Anne-Marie Beausoleil, Xiaojun Huang, Venkat R. Thalladi
  • Publication number: 20240128126
    Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.
    Type: Application
    Filed: November 20, 2023
    Publication date: April 18, 2024
    Inventors: Shu-Uei Jang, Chen-Huang Huang, Ryan Chia-Jen Chen, Shiang-Bau Wang, Shu-Yuan Ku
  • Patent number: 11961919
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
  • Publication number: 20240101667
    Abstract: Provided herein are methods and compositions for the identification of modulators of LILRB3 activation. Also provided herein are methods of treating cancer comprising the administration of an inhibitor LILRB3 activation. Also provided are methods of treating autoimmune disease or inhibiting the onset of transplant rejection or treating an inflammatory disorder comprising administering an agonist of LILRB3 activation to a subject.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 28, 2024
    Inventors: Chengcheng ZHANG, Guojin WU, Jaehyup KIM, Heyu CHEN, Mi DENG, Zhiqiang AN, Ningyan ZHANG, Ryan HUANG
  • Publication number: 20240082666
    Abstract: A golf club head includes a rear body having a crown member coupled to a sole member, and a front body coupled to the rear body to define a substantially hollow structure. The front body includes a strike face and a surrounding frame that extends rearward from a perimeter of the strike face. At least a portion of an outer wall of the club head comprises a thermoplastic composite having a plurality of lamina layers. The plurality of lamina layers include at least a fabric reinforced thermoplastic composite layer and a filled thermoplastic layer, and the fabric reinforced thermoplastic composite layer and the filled thermoplastic layer are directly bonded to each other without an intermediate adhesive.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Eric J. Morales, Ryan M. Stokke, Martin R. Jertson, Clayson C. Spackman, Cory S. Bacon, Yujen Huang, Travis D. Milleman
  • Publication number: 20240072156
    Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate, semiconductor channel sheets disposed over the semiconductor substrate, and source and drain regions located beside the semiconductor channel sheets. A gate structure is disposed between the source and drain regions and disposed over the semiconductor channel sheets. The gate structure laterally surrounds the semiconductor channel sheets. The gate structure includes a top gate electrode structure disposed above the semiconductor channel sheets, and lower gate electrode structures disposed between the semiconductor channel sheets. Sidewall spacers are disposed between the gate structure and source and drain regions, and the sidewall spacers located next to the top gate electrode structure have slant sidewalls.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen, Hsuan-Chih Wu
  • Patent number: 7612439
    Abstract: A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: November 3, 2009
    Assignee: Alpha and Omega Semiconductor Limited
    Inventors: Xiaotian Zhang, Argo Chang, James Lee, Ryan Huang, Kai Liu, Ming Sun
  • Publication number: 20090243729
    Abstract: Briefly, in accordance with one or more embodiments, a transimpedance amplifier of an optical transceiver or the like has a feedback element in a feedback arrangement and is capable of receiving an electrical current from an optical-to-electrical converter to generate an output voltage in response to the electrical current. A control circuit coupled to the feedback element is capable of providing a control signal to control a bias current of the transimpedance amplifier to maintain DC current flowing through the feedback element at or near zero by changing the bias current in response to the control circuit detecting a non-zero DC current flowing through the feedback element.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Miaobin Gao, Ryan Huang, Chien-Chang Liu
  • Publication number: 20070145609
    Abstract: A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 28, 2007
    Inventors: Xiaotian Zhang, Argo Chang, James Lee, Ryan Huang, Kai Liu
  • Patent number: D974198
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: January 3, 2023
    Assignee: Stanwood Imports
    Inventor: Weibiao Ryan Huang