Abstract: In one embodiment, a method is disclosed for extracting resistance from hierarchical circuit artwork having parent and child circuit blocks. In accordance with the method, and for each child block, at least one portion of signal trace artwork to which a parent circuit block may connect is identified; the identified portions of signal trace artwork are marked as deferred artwork; and resistance is extracted for the child circuit block less the deferred artwork. For each of the identified portions of signal trace artwork, a port is defined where deferred artwork adjoins artwork for which resistance has been extracted. For each parent circuit block, deferred artwork is promoted from child circuit blocks to which the parent circuit block connects; and resistance is extracted for the parent circuit block, including the promoted artwork.