Patents by Inventor Ryan L. Burns

Ryan L. Burns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622267
    Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: April 14, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Ryan L. Burns, Benjamen M. Rathsack, Mark H. Somervell, Makoto Muramatsu
  • Publication number: 20180096905
    Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 5, 2018
    Inventors: Ryan L. Burns, Benjamen M. Rathsack, Mark H. Somervell, Makoto Muramatsu
  • Patent number: 8796134
    Abstract: Methods of forming integrated circuit devices include forming first and second electrically conductive lines at side-by-side locations on an integrated circuit substrate. Steps are performed to selectively etch each of the first and second electrically conductive lines into a respective pair of interconnects having facing ends that are separated from each other. This selective etching step is performed using a photolithography mask having a modified-rectangular mask pattern thereon, which is configured to define a shape of the facing ends of each of the pair of interconnects.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: August 5, 2014
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation
    Inventors: Chang-Hwa Kim, Ryan L. Burns
  • Publication number: 20130210223
    Abstract: Methods of forming integrated circuit devices include forming first and second electrically conductive lines at side-by-side locations on an integrated circuit substrate. Steps are performed to selectively etch each of the first and second electrically conductive lines into a respective pair of interconnects having facing ends that are separated from each other. This selective etching step is performed using a photolithography mask having a modified-rectangular mask pattern thereon, which is configured to define a shape of the facing ends of each of the pair of interconnects.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 15, 2013
    Inventors: Chang-Hwa Kim, Ryan L. Burns
  • Patent number: 8302034
    Abstract: A solution for performing an optical proximity correction (OPC) process on a layout by incorporating a critical dimension (CD) correction is provided. A method may include separating the layout into a first portion and a second portion corresponding to the two exposures; creating a model for calculating a CD correction for a site on the first portion, the model corresponding to a topography change on the site due to the double exposures; implementing an OPC iteration for the fragment based on the model to generate an OPC solution for the first portion; and combining the OPC solution for the first portion with an OPC solution for the second portion to generate an OPC solution for the layout to generate a mask for fabricating a structure using the layout.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ryan L. Burns, Sean D. Burns
  • Patent number: 8084185
    Abstract: The present invention relates to planarization materials and methods of using the same for substrate planarization in photolithography. A planarization layer of a planarization composition is formed on a substrate. The planarization composition contains at least one aromatic monomer and at least one non-aromatic monomer. A substantially flat surface is brought into contact with the planarization layer. The planarization layer is cured by exposing to a first radiation or by baking. The substantially flat surface is then removed. A photoresist layer is formed on the planarization layer. The photoresist layer is exposed to a second radiation followed by development to form a relief image in the photoresist layer. The relief image is then transferred into the substrate.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Sean D. Burns, Colin J. Brodsky, Ryan L. Burns
  • Publication number: 20100199256
    Abstract: A solution for performing an optical proximity correction (OPC) process on a layout by incorporating a critical dimension (CD) correction is provided. A method may include separating the layout into a first portion and a second portion corresponding to the two exposures; creating a model for calculating a CD correction for a site on the first portion, the model corresponding to a topography change on the site due to the double exposures; implementing an OPC iteration for the fragment based on the model to generate an OPC solution for the first portion; and combining the OPC solution for the first portion with an OPC solution for the second portion to generate an OPC solution for the layout to generate a mask for fabricating a structure using the layout.
    Type: Application
    Filed: February 1, 2010
    Publication date: August 5, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ryan L. Burns, Sean D. Burns
  • Publication number: 20100173247
    Abstract: The present invention relates to planarization materials and methods of using the same for substrate planarization in photolithography. A planarization layer of a planarization composition is formed on a substrate. The planarization composition contains at least one aromatic monomer and at least one non-aromatic monomer. A substantially flat surface is brought into contact with the planarization layer. The planarization layer is cured by exposing to a first radiation or by baking The substantially flat surface is then removed. A photoresist layer is formed on the planarization layer. The photoresist layer is exposed to a second radiation followed by development to form a relief image in the photoresist layer. The relief image is then transferred into the substrate.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 8, 2010
    Applicant: International Business Machines Corporation
    Inventors: Sean D. Burns, Colin J. Brodsky, Ryan L. Burns
  • Patent number: 7160356
    Abstract: A polymeric composite may be used for forming fluid separation membranes. The membranes may be formed from polyimide, polyamide or poly (pyrrolone-imide) materials. Polyamides may be formed by the condensation of a tetraamine, a tetraacid, and a diamine. Polyimides and poly (pyrrolone-imides) may be formed by the cyclization of a polymer precursor. A polymeric composite may include a dithiolene or a mixture of dithiolenes. A polymer matrix incorporating dithiolenes may exhibit an olefin/paraffin solubility selectivity. A solubility selectivity may be between about 1.1 and about 2.0.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: January 9, 2007
    Assignee: Board of Regents, The University of Texas System
    Inventors: William J. Koros, Ryan L. Burns
  • Patent number: 6602415
    Abstract: A polymeric composite may be used for forming fluid separation membranes. The fluid separation membranes may go through a separation selectivity maximum as a function of operating conditions (e.g., temperature and/or pressure). The membranes may be formed from polyamide or poly (pyrrolone-imide). Polyamides may be formed by the condensation of a tetraamine, a tetraacid, and a diamine. Poly (pyrrolone-imides) may be formed by the condensation of a polyamide.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: August 5, 2003
    Assignee: Board of Regents, The University of Texas
    Inventors: William J. Koros, Ryan L. Burns
  • Publication number: 20020153315
    Abstract: A polymeric composite may be used for forming fluid separation membranes. The fluid separation membranes may go through a separation selectivity maximum as a function of operating conditions (e.g., temperature and/or pressure). The membranes may be formed from polyamide or poly (pyrrolone-imide). Polyamides may be formed by the condensation of a tetraamine, a tetraacid, and a diamine. Poly (pyrrolone-imides) may be formed by the condensation of a polyamide.
    Type: Application
    Filed: February 9, 2001
    Publication date: October 24, 2002
    Inventors: William J. Koros, Ryan L. Burns