Abstract: A package comprising a metallization portion; an integrated device coupled to the metallization portion; a substrate; a plurality of wire bonds coupled to the substrate and the metallization portion; and an encapsulation layer coupled to the metallization portion, wherein the encapsulation layer at least partially encapsulates the integrated device, the plurality of wire bonds and the substrate.

Abstract: A package comprising a first integrated device; a second integrated device; and a package interposer coupled to the first integrated device and the second integrated device. The package interposer comprises a first metallization portion; a second metallization portion; a first encapsulation layer coupled to the first metallization portion and the second metallization portion; and a passive device located at least partially in the first encapsulation layer. The first encapsulation layer and the passive device are located between the first metallization portion and the second metallization portion.

Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate; a second substrate; a second integrated device coupled to the second substrate; and a heat sink coupled to the second substrate, wherein the heat sink vertically overlaps with at least part of the first integrated device, and wherein the heat sink is located laterally to the second integrated device.

Abstract: A stacked IC device includes a first memory stack including two or more memory dies coupled to a substrate and a second memory stack including two or more memory dies coupled to the substrate. The stacked IC device also includes a logic die electrically connected to memory dies of the first memory stack through face-to-face connections to a top die of the first memory stack and electrically connected to memory dies of the second memory stack through face-to-face connections to a top die of the second memory stack. The stacked IC device further includes a patch component disposed in a region between the first memory stack and the second memory stack. The patch component includes conductors that electrically connect the logic die to the substrate.

Abstract: A package comprising a first integrated device; an interposer coupled to the first integrated device; a passive device coupled to the first integrated device; a plurality of post interconnects coupled to the first integrated device; a second integrated device coupled to the interposer, the passive device and the plurality of post interconnects; and an encapsulation layer located between the first integrated device and the second integrated device.

Abstract: A package comprising a first metallization portion; a first integrated device coupled to the first metallization portion; a bridge coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion; a second metallization portion coupled to the bridge and the encapsulation layer, such that the first integrated device, the bridge and the encapsulation layer are located between the first metallization portion and the second metallization portion, and a second integrated device coupled to the second metallization portion, wherein the second integrated device and the bridge at least partially vertically overlap.

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects located at least partially in the at least one dielectric layer. The frame may be an embedded frame.

Abstract: A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

Abstract: Disclosed is a semiconductor device. In an aspect, a semiconductor device includes: a first-tier passive device including a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and one or more second-tier passive devices disposed over the first-tier passive device. Each one of the one or more second-tier passive devices includes: a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and a set of through substrate vias (TSVs) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion. The semiconductor device comprises a passive component including the passive device portion of the first-tier passive device electrically coupled to one or more passive device portions of the one or more second-tier passive devices through the metallization portions of the first-tier passive device and the one or more second-tier passive devices.

Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

Abstract: Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods are also disclosed. The cavity of the core (that has one or more core layers) of the substrate includes an embedded electrical device structure that an electrical device built upon another second component(s) to make the overall height of the electrical device structure compatible with the height of the cavity of the core. In this manner, the design criteria used to select thickness or height of the core for providing the desired stability in the substrate can be incompatible with the thickness or the height of the embedded electrical device.

Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Abstract: A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Abstract: A device that includes a board, a package and a patch substrate. The board includes a cavity. The package is coupled to a first side of the board. The package includes a substrate and an integrated device coupled to the substrate. The integrated device is located at least partially in the cavity of the board. The patch substrate is coupled to a second side of the board. The patch substrate is located over the cavity of the board. The patch substrate is configured as an electromagnetic interference (EMI) shield for the package.

Abstract: An integrated circuit (IC) package is described. The IC package includes a package die and die interconnects on an active surface of the package die. The IC package also includes an integrated passive device (IPD) coupled to the active surface of the package die, between the plurality of die interconnects. A portion of the IPD extends beyond a Z-height of the die interconnects. The IC package further includes a package substrate coupled to the die interconnects, the package substrate having a cavity to receive the portion of the IPD.