Abstract: Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

Abstract: The present disclosure provides a method of manufacturing a headrest stay formed end. The method includes cutting teeth on the insertion end of a headrest stay and pressing the teeth inwardly to form a chamfered endform on the insertion end. A headrest stay having a chamfered endform comprising a plurality of curved teeth is also provided.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

Abstract: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion.

Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Abstract: Embodiments of the hybrid thermal-chromatograph systems described herein solve the co-product generation problem associated with seawater desalination, and result in significant reduction in the selling price of fresh water generated through the process, while also solving problems associated with traditional lithium mining practices.

Abstract: In embodiments of the invention, the invention comprises a light tip cable including a cartridge assembly affixed to a medial end of the cable, the cartridge assembly including an emitter housing where the emitter housing includes an opening at a medial end of the housing and a flange at a lateral end of the housing. In embodiments of the invention, the cartridge assembly includes a light emitting element in the housing extending to the opening, retention features covering at least a portion of the housing, including the flange, the retention features comprising a lateral face and a lobe and at least one load bearing strand extending from the cable to the emitter; and electrical connectors extending from the cable to the light emitting element.

Abstract: A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

Abstract: In embodiments of the invention, the invention comprises a light tip cable including a cartridge assembly affixed to a medial end of the cable, the cartridge assembly including an emitter housing where the emitter housing includes an opening at a medial end of the housing and a flange at a lateral end of the housing. In embodiments of the invention, the cartridge assembly includes a light emitting element in the housing extending to the opening, retention features covering at least a portion of the housing, including the flange, the retention features comprising a lateral face and a lobe and at least one load bearing strand extending from the cable to the emitter; and electrical connectors extending from the cable to the light emitting element.

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Abstract: A device that includes a board, a package and a patch substrate. The board includes a cavity. The package is coupled to a first side of the board. The package includes a substrate and an integrated device coupled to the substrate. The integrated device is located at least partially in the cavity of the board. The patch substrate is coupled to a second side of the board. The patch substrate is located over the cavity of the board. The patch substrate is configured as an electromagnetic interference (EMI) shield for the package.

Abstract: In embodiments of the invention, the invention comprises a light tip cable including a cartridge assembly affixed to a medial end of the cable, the cartridge assembly including an emitter housing where the emitter housing includes an opening at a medial end of the housing and a flange at a lateral end of the housing. In embodiments of the invention, the cartridge assembly includes a light emitting element in the housing extending to the opening, retention features covering at least a portion of the housing, including the flange, the retention features comprising a lateral face and a lobe and at least one load bearing strand extending from the cable to the emitter; and electrical connectors extending from the cable to the light emitting element.

Abstract: An integrated circuit (IC) package is described. The IC package includes a package die and die interconnects on an active surface of the package die. The IC package also includes an integrated passive device (IPD) coupled to the active surface of the package die, between the plurality of die interconnects. A portion of the IPD extends beyond a Z-height of the die interconnects. The IC package further includes a package substrate coupled to the die interconnects, the package substrate having a cavity to receive the portion of the IPD.

Abstract: A device that includes a board, a package and a patch substrate. The board includes a cavity. The package is coupled to a first side of the board. The package includes a substrate and an integrated device coupled to the substrate. The integrated device is located at least partially in the cavity of the board. The patch substrate is coupled to a second side of the board. The patch substrate is located over the cavity of the board. The patch substrate is configured as an electromagnetic interference (EMI) shield for the package.

Abstract: A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

Abstract: An ear tip for use with a hearing aid is described, wherein the ear tip may include one or more features adapted to improve the comfort and or other characteristics of the ear tip.

Abstract: An ear tip for use with a hearing aid is described, wherein the ear tip may include one or more features adapted to improve the comfort and or other characteristics of the ear tip.

Abstract: In embodiments of the invention, the invention comprises a light tip cable including a cartridge assembly affixed to a medial end of the cable, the cartridge assembly including an emitter housing where the emitter housing includes an opening at a medial end of the housing and a flange at a lateral end of the housing. In embodiments of the invention, the cartridge assembly includes a light emitting element in the housing extending to the opening, retention features covering at least a portion of the housing, including the flange, the retention features comprising a lateral face and a lobe and at least one load bearing strand extending from the cable to the emitter; and electrical connectors extending from the cable to the light emitting element.

Abstract: An ear tip for use with a hearing aid is described, wherein the ear tip may include one or more features adapted to improve the comfort and or other characteristics of the ear tip.