Abstract: Systems and methods for antenna impedance matching provide an integrated circuit (IC) configured to be placed proximate an antenna that includes a sensor based on a coupler having forward and reverse power detectors for detecting an impedance at the antenna and provides dynamic impedance matching. Further, exemplary aspects of the present disclosure contemplate using a single wire bus capable of supplying power and providing a bidirectional serial communication link to allow communication between the IC of the present disclosure and a control circuit (e.g., a bridge or transceiver). Further aspects of the present disclosure contemplate providing systems and methods for calibrating the IC at production. Further, the accuracy of the impedance sensor may be dependent on accurate determination of power and phase difference between forward and reverse coupled signals, and a system for removing an offset between the forward and reverse power detectors is disclosed.

Abstract: A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

Abstract: Systems and methods for antenna impedance matching provide an integrated. circuit (IC) configured to be placed proximate an antenna that includes a sensor based on a coupler having forward and reverse power detectors for detecting an impedance at the antenna and provides dynamic impedance matching. Further, exemplary aspects of the present disclosure contemplate using a single wire bus capable of supplying power and providing a bidirectional serial communication link to allow communication between the IC of the present disclosure and a control circuit (e.g., a bridge or transceiver). Further aspects of the present disclosure contemplate providing systems and methods for calibrating the IC at production. Further, the accuracy of the impedance sensor may be dependent on accurate determination of power and phase difference between forward and. reverse coupled signals, and a system for removing an offset between the forward and reverse power detectors is disclosed.

Abstract: A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or “one shot” accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.

Abstract: A time-to-digital converter (TDC) detects a timing relationship between signals representing two temporal events. Several samples are acquired over a certain time period for each event, and the signals related to the different events are digitized or quantized either by separate TDCs or by a single TDC in a time-sequential manner. The quantized results are then processed, for example added to/ subtracted from one another, and used to determine the phase or time difference between the two events. When information being quantized is quasi-static over time periods where the measurement is performed, the instantaneous or “one shot” accuracy of a TDC need not be as good as or better than the desired time resolution. Digitally processing the signals and averaging the results moves an otherwise difficult analog quantizer problem to the digital domain where savings in power and chip area can be easily achieved without sacrificing accuracy.

Abstract: A charge pump phase-locked loop circuit includes an active loop filter, an adjustable reference voltage source, and a charge pump. The active loop filter includes an amplifier that has a negative input node, a positive input node, and an output node. The adjustable reference voltage source is coupled to the positive input node to provide an adjustable reference voltage. The charge pump is coupled to the negative input node to provide a current to or draw a current from the active loop filter in response to a signal from a phase detector. The charge pump includes a first current source coupled to a first voltage and a second current source electrically coupled to a second voltage, the second current source including a resistor. The second current source is configured such that a current provided by the second current source depends on a resistance value of the resistor and a difference between the reference voltage and the second voltage.

Abstract: A charge pump phase-locked loop circuit includes an active loop filter, an adjustable reference voltage source, and a charge pump. The active loop filter includes an amplifier that has a negative input node, a positive input node, and an output node. The adjustable reference voltage source is coupled to the positive input node to provide an adjustable reference voltage. The charge pump is coupled to the negative input node to provide a current to or draw a current from the active loop filter in response to a signal from a phase detector. The charge pump includes a first current source coupled to a first voltage and a second current source electrically coupled to a second voltage, the second current source including a resistor. The second current source is configured such that a current provided by the second current source depends on a resistance value of the resistor and a difference between the reference voltage and the second voltage.

Abstract: The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode. This loop works by comparing the output voltage of the FLL DAC to the LPF output voltage, and then using this value to modulate the divider's dividing value. After the secondary feedback loop settles, output voltage from the LPF will be equal to the value that can drive the VCO to the desired lock frequency, and the phase error at the input side of the PFD produces a zero-average current to the charge pump. When this condition is set, the loop is essentially already in phase lock and the lock transient from the FLL mode to the PLL mode will be minimal.

Abstract: The current invention provides a second feedback loop around the existing FLL, which forces the signal on the route of N-divider (NDIV), PFD, CP, and LPF to essentially reach their desired lock conditions before the FLL is switched off and the system enters PLL mode. This loop works by comparing the output voltage of the FLL DAC to the LPF output voltage, and then using this value to modulate the divider's dividing value. After the secondary feedback loop settles, output voltage from the LPF will be equal to the value that can drive the VCO to the desired lock frequency, and the phase error at the input side of the PFD produces a zero-average current to the charge pump. When this condition is set, the loop is essentially already in phase lock and the lock transient from the FLL mode to the PLL mode will be minimal.

Abstract: A fractional-N based Automatic Frequency Control (AFC) system for a mobile terminal is provided. In general, automatic frequency control is implemented in a frequency synthesizer to correct or compensate for a frequency error of an associated reference oscillator. The frequency synthesizer includes a first fractional-N phase-locked loop (FN-PLL) generating a baseband clock signal used by a baseband processor of the mobile terminal, a second FN-PLL generating a receiver local oscillator signal used by a receiver of the mobile terminal to downconvert a received radio frequency signal to a desired frequency, and a translational PLL generating a transmitter local oscillator signal used by a transmitter of the mobile terminal to provide a radio frequency transmit signal. The automatic frequency control is performed by applying a digital correction value, which is preferably multiplicative, to fractional-N dividers of the first and second FN-PLLs.

Abstract: A linearization system is provided for a Fractional-N Offset Phase Locked Loop (FN-OPLL) in a frequency or phase modulation system. In general, the linearization system processes a modulation signal to provide a linearized modulation signal to a fractional-N divider in a reference path of the FN-OPLL such that a frequency or phase modulation component at the output of the FN-OPLL is substantially linear with respect to the modulation signal.

Abstract: A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.

Abstract: A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.

Abstract: The present invention provides a system for adjusting a selectable capacitance of a variable capacitance array to compensate for voltage non-linearity of the variable capacitance array. In general, the system includes the variable capacitance array and a calibration circuit. The calibration circuit operates to determine a voltage across the variable capacitance array and to generate a capacitance selection signal based on the voltage across the variable capacitance array and a known capacitance versus voltage characteristic of the variable capacitance array.