Patents by Inventor Ryan Lobo

Ryan Lobo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11644493
    Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: May 9, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Saurabh Singh, Chandra B. Prakash, Eric Kimball, Cory J. Peterson, Ryan Lobo
  • Publication number: 20230003779
    Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.
    Type: Application
    Filed: February 10, 2022
    Publication date: January 5, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Saurabh SINGH, Chandra B. PRAKASH, Eric KIMBALL, Cory J. PETERSON, Ryan LOBO
  • Publication number: 20190235050
    Abstract: A radar sensing system includes a transmitter and a receiver. The transmitter is configured for installation and use in a vehicle and configured to transmit radio signals. The receiver is configured for installation and use in the vehicle and configured to receive radio signals that include the transmitted radio signals transmitted by the transmitter and reflected from objects in an environment. The receiver includes a plurality of inputs and a plurality of low noise amplifiers (LNAs). Each input of the plurality of inputs is communicatively coupled to a corresponding LNA of the plurality of LNAs. The plurality of LNAs are co-located, and respective outputs of the plurality of LNAs are all directly coupled together at a connection point.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 1, 2019
    Inventors: James Maligeorgos, Aria Eshraghi, Ryan Lobo, Lysander Lim, Vito Giannini, Marius Goldenberg
  • Patent number: 8659457
    Abstract: Cost-effective structures and methods that allow an integrated digital-to-analog converter (DAC) to simultaneously achieve wide dynamic ranges and bandwidths through the use of built-in measurement and compensation mechanisms that are primarily digital. The measurements of the DAC's distortions are made with a relatively simple analog-to-digital converter (ADC) that is not designed to accommodate the combination of the bandwidth and the resolution offered by the DAC, but is nonetheless sufficient in determining the characteristics of the DAC's impairments during a calibration procedure. This information is then used in a feed-forward compensation system during the DAC's normal operation to estimate and cancel the distortions in its output signal that could result from the various impairments.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: February 25, 2014
    Assignee: XW, LLC.
    Inventors: Oren E. Eliezer, Ryan Lobo, Mark Appel
  • Publication number: 20130234871
    Abstract: Cost-effective structures and methods that allow an integrated digital-to-analog converter (DAC) to simultaneously achieve wide dynamic ranges and bandwidths through the use of built-in measurement and compensation mechanisms that are primarily digital. The measurements of the DAC's distortions are made with a relatively simple analog-to-digital converter (ADC) that is not designed to accommodate the combination of the bandwidth and the resolution offered by the DAC, but is nonetheless sufficient in determining the characteristics of the DAC's impairments during a calibration procedure. This information is then used in a feed-forward compensation system during the DAC's normal operation to estimate and cancel the distortions in its output signal that could result from the various impairments.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 12, 2013
    Applicant: XW, LLC d/b/a Xtendwave
    Inventors: Oren E. Eliezer, Ryan Lobo, Mark Appel
  • Patent number: 8406723
    Abstract: Systems and methods which provide DC current path circuitry, such as for providing a DC bias, in association with a filter circuit such that parasitic attributes of the DC current path circuitry combines with the filter component attributes are shown. According to embodiments, the parasitic attributes of the DC current path circuitry components are added into the associated filter circuit network design. A parasitic capacitance of the DC current path circuitry may, for example, be aggregated with a capacitor of the filter circuit to eliminate or mitigate the effect of the presence of the DC current path circuitry on the associated filter frequency response. Embodiments implement an active inductor configuration for providing a DC current path in association with a filter circuit. An active inductor of embodiments is provided using a transistor, appropriately biased to actively exhibit low impedance at DC and high impedance at RF frequencies.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 26, 2013
    Assignee: CSR Technology Inc.
    Inventors: Ryan Lobo, Timothy M. Magnusen
  • Publication number: 20060105731
    Abstract: A method is provided for reducing a DC bias in a receiver. This method includes isolating a second circuit portion from a first circuit portion (535) and determining a second DC bias correction value for the second circuit portion that will eliminate a second DC bias at the isolated second circuit portion (540). The second circuit portion is then connected to the first circuit portion (550) and a bias-maximizing code word is generated at the first circuitry (505). A first DC bias correction value is then determined that will eliminate a first DC bias at the first circuit portion (555). The bias-maximizing code word is formed such that: a first integrated value of a first half of the bias-maximizing code word has a positive value, and a second integrated value of a second half of the bias-maximizing code word over half of the code word length has a negative value.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 18, 2006
    Inventors: Terence Johnson, Nitin Sharma, Ryan Lobo