Patents by Inventor Ryan M. Martin

Ryan M. Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10170679
    Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode, the second portion of the second superconductor electrode contacting the substrate on at least one side of the spacer.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Ryan M. Martin, Jeffrey W. Sleight
  • Patent number: 9929334
    Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Ryan M. Martin, Jeffrey W. Sleight
  • Publication number: 20180040800
    Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode, the second portion of the second superconductor electrode contacting the substrate on at least one side of the spacer.
    Type: Application
    Filed: October 18, 2017
    Publication date: February 8, 2018
    Inventors: Josephine B. Chang, Michael A. Guillorn, Ryan M. Martin, Jeffrey W. Sleight
  • Publication number: 20160211438
    Abstract: Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit may comprise: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 21, 2016
    Inventors: Josephine B. Chang, Michael A. Guillorn, Ryan M. Martin, Jeffrey W. Sleight
  • Publication number: 20150255281
    Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 10, 2015
    Inventors: Robert L. Bruce, Cheng-Wei Cheng, Joel P. de Souza, Ryan M. Martin, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9018084
    Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Chung-Hsun Lin, Ryan M. Martin, Jeffrey W. Sleight
  • Publication number: 20150048423
    Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.
    Type: Application
    Filed: September 17, 2013
    Publication date: February 19, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Bruce, Cheng-Wei Cheng, Joel P. de Souza, Ryan M. Martin, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20150048422
    Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Bruce, Cheng-Wei Cheng, Joel P. de Souza, Ryan M. Martin, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 8937299
    Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Cheng-Wei Cheng, Amlan Majumdar, Ryan M. Martin, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20140308806
    Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.
    Type: Application
    Filed: September 9, 2013
    Publication date: October 16, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Chung-Hsun Lin, Ryan M. Martin, Jeffrey W. Sleight
  • Publication number: 20140306286
    Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.
    Type: Application
    Filed: April 10, 2013
    Publication date: October 16, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Chung-Hsun Lin, Ryan M. Martin, Jeffrey W. Sleight
  • Publication number: 20140264607
    Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Cheng-Wei Cheng, Amlan Majumdar, Ryan M. Martin, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20140264446
    Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.
    Type: Application
    Filed: August 14, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: ANIRBAN BASU, CHENG-WEI CHENG, AMLAN MAJUMDAR, RYAN M. MARTIN, UZMA RANA, DEVENDRA K. SADANA, KUEN-TING SHIU, YANNING SUN
  • Patent number: 8449781
    Abstract: The present disclosure relates to a method for selectively etching-back a polymer matrix to expose tips of carbon nanotubes comprising: a. growing carbon nanotubes on a conductive substrate; b. filling the gap around the carbon nanotubes with a polymeric fill matrix comprising at least one latent photoacid generator; and c. selectively etching-back the polymeric fill matrix to expose tips of the carbon nanotubes.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: May 28, 2013
    Assignee: International Business Machines Corporation
    Inventors: Maxime Darnon, Gerald W. Gibson, Pratik P. Joshi, Ryan M. Martin, Ying Zhang
  • Publication number: 20120193680
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian Ulrich Engelmann, Nicholas C.M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Publication number: 20120193715
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian Ulrich Engelmann, Nicholas C.M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Patent number: 8232171
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sebastian Ulrich Engelmann, Nicholas C. M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Publication number: 20110311825
    Abstract: The present disclosure relates to a method for selectively etching-back a polymer matrix to expose tips of carbon nanotubes comprising: a. growing carbon nanotubes on a conductive substrate; b. filling the gap around the carbon nanotubes with a polymeric fill matrix comprising at least one latent photoacid generator; and c. selectively etching-back the polymeric fill matrix to expose tips of the carbon nanotubes.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 22, 2011
    Applicant: International Business Machines Corp.
    Inventors: Maxime Darnon, Gerald W. Gibson, Pratik P. Joshi, Ryan M. Martin, Ying Zhang
  • Publication number: 20110062494
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian Ulrich Engelmann, Nicholas C.M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang