Patents by Inventor Ryan M. Mitchell

Ryan M. Mitchell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7718231
    Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 18, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kwang Su Choe, Keith E. Fogel, Siegfried L. Maurer, Ryan M. Mitchell, Devendra K. Sadana
  • Patent number: 7247546
    Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 ? thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: July 24, 2007
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Huajie Chen, Keith Fogel, Ryan M. Mitchell, Devendra K. Sadana
  • Patent number: 7071103
    Abstract: The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: July 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Huajie Chen, Michael A. Gribelyuk, Judson R. Holt, Woo-Hyeong Lee, Ryan M. Mitchell, Renee T. Mo, Dan M. Mocuta, Werner A. Rausch, Paul A. Ronsheim, Henry K. Utomo