Patents by Inventor Ryan M. Nett

Ryan M. Nett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processing system to implement wiring/silicon blockages via parameterized cells
    Patent number: 10372866
    Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Berry, Adam R. Jatkowski, Frank Malgioglio, Ryan M. Nett, Joseph J. Palumbo, Sean Salisbury, Gerald L. Strevig, III
  • DATA PROCESSING SYSTEM TO IMPLEMENT WIRING/SILICON BLOCKAGES VIA PARAMETERIZED CELLS
    Publication number: 20180232481
    Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.
    Type: Application
    Filed: February 13, 2017
    Publication date: August 16, 2018
    Inventors: Christopher J. Berry, Adam R. Jatkowski, Frank Malgioglio, Ryan M. Nett, Joseph J. Palumbo, Sean Salisbury, Gerald L. Strevig, III