Patents by Inventor Ryan Mesch

Ryan Mesch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260141840
    Abstract: An electronic device may have a display. The display may include an array of pixels formed on a display panel. A system-in-package (SiP) may include a substrate, electronic components mounted on the substrate, and mold material that overlaps and conforms to the electronic components. A portion of the substrate that is not overlapped by the mold material may be bonded to the display panel. The electronic components mounted on the substrate of the SiP may include a timing controller integrated circuit and/or a display driver integrated circuit. A plurality of display driver integrated circuit chiplets may be mounted on the substrate of the SiP. The substrate of the SiP may be electrically connected to the display panel by side-wrapped conductive traces. The substrate of the SiP may have portions with different thicknesses.
    Type: Application
    Filed: October 15, 2025
    Publication date: May 21, 2026
    Inventors: Anshi Liang, Cheng-Chih Hsieh, Flynn P. Carson, Han-Chieh Chang, Job Nalianya, Jonas Hsu, Joshua G. Wurzel, Junnan Zhao, Ka Kuen Wan, Kasra M. Omid-Zohoor, Ken Hsuan Liao, Kumar Nagarajan, Lingqi Wu, Marc J. DeVincentis, Martin R. Kardasz, Paolo Sacchetto, Pierpaolo Lupo, Po-Jui Chen, Ryan Mesch, Shin-Hung Yeh, Shreyas Tater, Sinan Alousi, Snehal T. Jariwala, Tsung-Ting Tsai, Victor H. Yin, Wei H. Yao, Ying-Chih Wang, Yong Wang
  • Patent number: 12494433
    Abstract: Improved redistribution layer structures for integrated circuit or system-on-chip (SoC) packages substrate are disclosed. Via landing pads and via interconnects in the redistribution layers are self-aligning with the centers of the vias aligning with the pads. This self-alignment may allow pads that terminate non-stacked vias to have decreased widths or diameters without extra capture space. The redistribution layers have vias with vertical or near vertical sidewalls. Vias may also have various shapes, widths, or lengths. Traces in the redistribution layers may have various lengths and shapes with lengths that may extend into layers routing the vias to provide increased metal density in the traces.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: December 9, 2025
    Assignee: Apple Inc.
    Inventors: Ryan Mesch, Jun Chung Hsu
  • Publication number: 20230402390
    Abstract: Improved redistribution layer structures for integrated circuit or system-on-chip (SoC) packages substrate are disclosed. Via landing pads and via interconnects in the redistribution layers are self-aligning with the centers of the vias aligning with the pads. This self-alignment may allow pads that terminate non-stacked vias to have decreased widths or diameters without extra capture space. The redistribution layers have vias with vertical or near vertical sidewalls. Vias may also have various shapes, widths, or lengths. Traces in the redistribution layers may have various lengths and shapes with lengths that may extend into layers routing the vias to provide increased metal density in the traces.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Inventors: Ryan Mesch, Jun Chung Hsu