Patents by Inventor Ryan Meyer
Ryan Meyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12268751Abstract: Provided are novel anti-?v?6 antibodies and antibody-drug conjugates and methods of using such anti-?v?6 antibodies and antibody-drug conjugates to treat cancer.Type: GrantFiled: October 18, 2023Date of Patent: April 8, 2025Assignee: Seagen Inc.Inventors: Maureen Ryan, Lori Westendorf, Eric Bradley Meyer, Heather Jean Kostner
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Patent number: 12270347Abstract: An air turbine starter for starting an engine includes a starter housing having an inlet, an outlet, and a flow path extending between the inlet and the outlet. The air turbine starter includes a rotatable turbine member having a central hub defining a platform and a set of blades extending radially from the platform. The air turbine starter also includes a damping member.Type: GrantFiled: April 25, 2023Date of Patent: April 8, 2025Assignee: Unison Industries, LLCInventors: Shiloh Montegomery Meyers, Steven Ryan Kerley, Thomas V Ng
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Patent number: 12251627Abstract: Disclosed is a system for controlling a robot via a foot-operable controller. The foot-operable controller includes a grid of large pressure-sensitive tiles that are responsive to being stepped on. Signals from the pressure-sensitive tiles are provided to a controller interface that converts the signals to control messages compatible with existing robot control interfaces, such as a universal serial bus. The foot-operable controller may be used to control various robots, including for example a robot equipped with a claw arm or a robot equipped with a ring launcher.Type: GrantFiled: February 22, 2022Date of Patent: March 18, 2025Assignee: Cardinal Gibbons High SchoolInventors: Grant Christian Ozaki, Benjamin James Miranda, Thomas Ryan Michael Greene, Brett Matthew Lopez, Charles Joseph Kilani, William Michael Meyers, Grace Ann Eberle, Ian Setia, Joseph Michael Biersack, Joseph Andrew Milazzo, Brett Richard Gallagher, Cassian Farias Kraus, Nicole Carol Allen, Kevin Nicolas Haller
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Patent number: 12177295Abstract: Techniques for providing network applications are described. For instance, system(s) may install a network application onto a virtual server. While installing the network application, the system(s) may monitor the installation in order to identify events. The system(s) may then generate a first file that includes file events, a second file that includes registry events, and a third file that includes service events. Additionally, the system may copy the software files installed on the virtual server. The system(s) may then generate a software package that includes the files and store the software package on a virtual storage device. After storing the software package, the system(s) may make copies of the software package and store the copies on multiple virtual storage devices. The system(s) may then use the virtual storage devices to install and launch the network application on virtual servers.Type: GrantFiled: March 30, 2021Date of Patent: December 24, 2024Assignee: Amazon Technologies, Inc.Inventors: Justin Maneri, Brian Fisher, Jake Matthew Kulanko, Arjuna Baratham, Ryan Meyer, Mickey Ottis Williams
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Patent number: 11937429Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.Type: GrantFiled: December 20, 2021Date of Patent: March 19, 2024Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
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Patent number: 11549437Abstract: A combustor for a gas turbine engine includes an outer liner having a first end interconnected to an opposite second end by an outer liner wall composed of a plurality of outer segments. The inner liner has a first inner end interconnected to an opposite second inner end by an inner liner wall composed of a plurality of inner segments. The outer liner wall and the inner liner wall define a combustion chamber, and each of the outer wall segments extend at an angle of at least 40 degrees relative to a longitudinal axis. The outer wall segments includes a first segment, a second segment that extends at a second angle relative to the first segment, which is less than a third angle defined between the second segment and a third segment and is substantially the same as a fourth angle defined between the third segment and a fourth segment.Type: GrantFiled: February 18, 2021Date of Patent: January 10, 2023Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Rodolphe Dudebout, Hamdullah Ozogul, Atul Verma, Amy Kujala, Michael Wedig, Ryan Meyer, Bradley Culbertson
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Publication number: 20220400344Abstract: Example techniques relate to device spaces and default designations in a media playback system. A device space may create an association between a networked microphone device and one or more playback devices such that certain voice commands (e.g., playback commands) received by the networked microphone device are used to control the one or more playback devices (unless otherwise designated in the voice command). Furthermore, in bonded pairs and bonded groups of playback devices that include at least one NMD, certain playback devices within the bonded pair or group may be designated as default so as to avoid multiple responses to a voice input.Type: ApplicationFiled: May 23, 2022Publication date: December 15, 2022Inventors: Sein Woo, Andrew Lindley, Ryan Meyers
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Publication number: 20220260016Abstract: A combustor for a gas turbine engine includes an outer liner having a first end interconnected to an opposite second end by an outer liner wall composed of a plurality of outer segments. The inner liner has a first inner end interconnected to an opposite second inner end by an inner liner wall composed of a plurality of inner segments. The outer liner wall and the inner liner wall define a combustion chamber, and each of the outer wall segments extend at an angle of at least 40 degrees relative to a longitudinal axis. The outer wall segments includes a first segment, a second segment that extends at a second angle relative to the first segment, which is less than a third angle defined between the second segment and a third segment and is substantially the same as a fourth angle defined between the third segment and a fourth segment.Type: ApplicationFiled: February 18, 2021Publication date: August 18, 2022Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Rodolphe Dudebout, Hamdullah Ozogul, Atul Verma, Amy Kujala, Michael Wedig, Ryan Meyer, Bradley Culbertson
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Patent number: 11343614Abstract: Example techniques relate to device spaces and default designations in a media playback system. A device space may create an association between a networked microphone device and one or more playback devices such that certain voice commands (e.g., playback commands) received by the networked microphone device are used to control the one or more playback devices (unless otherwise designated in the voice command). Furthermore, in bonded pairs and bonded groups of playback devices that include at least one NMD, certain playback devices within the bonded pair or group may be designated as default so as to avoid multiple responses to a voice input.Type: GrantFiled: January 31, 2019Date of Patent: May 24, 2022Assignee: Sonos, Inc.Inventors: Sein Woo, Andrew Lindley, Ryan Meyers
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Publication number: 20220115401Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Applicant: Micron Technology, Inc.Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
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Patent number: 11239252Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.Type: GrantFiled: June 22, 2020Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
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Patent number: 10946704Abstract: A railroad trailer chassis comprising two or more road axles, two or more rail axles operable to be moved between first and second positions, and a work unit. The railroad trailer chassis is operable to be driven or towed in a road mode when the two or rail axles are in their respective first positions. The railroad trailer chassis is operable to be driven or towed in a rail mode when the two or more rail axles are in their respective second positions. The work unit is operable to perform one or more railroad maintenance or operation functions when driven in the rail mode.Type: GrantFiled: February 12, 2018Date of Patent: March 16, 2021Assignee: HARSCO TECHNOLOGIES LLCInventors: Ryan Meyer, Robert R. Schrunk, III
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Patent number: 10848522Abstract: A JIT service in a cloud computing environment manages just-in-time access to resources in the cloud computing environment for an external device. When JIT access to a resource is requested by a device, the JIT service retrieves a JIT policy for the resource that includes screening criteria limiting automatic granting of JIT access to users who meet the screening criteria. Screening information for a user associated with the request is evaluated against one or more screening requirements set forth by the screening criteria. If the screening criteria and any other criteria of the JIT policy are satisfied, the JIT service provisions JIT access to the resource for the device.Type: GrantFiled: October 14, 2019Date of Patent: November 24, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ramnath Prasad, Pradeep Ayyappan Nair, Veena Ramachandran, Sandeep Kalarickal, Thomas Knudson, Pavan Gopal Bandla, Chetan Shankar, Ranajoy Sanyal, Qingsu Wu, Chi Zhou, Doug Kirschner, Ryan Meyer, Thomas Keane
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Publication number: 20200366992Abstract: Example techniques relate to device spaces and default designations in a media playback system. A device space may create an association between a networked microphone device and one or more playback devices such that certain voice commands (e.g., playback commands) received by the networked microphone device are used to control the one or more playback devices (unless otherwise designated in the voice command). Furthermore, in bonded pairs and bonded groups of playback devices that include at least one NMD, certain playback devices within the bonded pair or group may be designated as default so as to avoid multiple responses to a voice input.Type: ApplicationFiled: January 31, 2019Publication date: November 19, 2020Inventors: Sein Woo, Andrew Lindley, Ryan Meyers
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Publication number: 20200321352Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Applicant: Micron Technology, Inc.Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
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Patent number: 10727242Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.Type: GrantFiled: April 2, 2019Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Kunal R. Parekh, Matthew Park, Joseph Neil Greeley, Chet E. Carter, Martin C. Roberts, Indra V. Chary, Vinayak Shamanna, Ryan Meyer, Paolo Tessariol
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Patent number: 10720446Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.Type: GrantFiled: October 11, 2018Date of Patent: July 21, 2020Assignee: Micron Technology, Inc.Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
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Patent number: 10586807Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material.Type: GrantFiled: June 11, 2019Date of Patent: March 10, 2020Assignee: Micron Technology, Inc.Inventors: Zhiqiang Xie, Chris M. Carlson, Justin B. Dorhout, Anish A. Khandekar, Greg Light, Ryan Meyer, Kunal R. Parekh, Dimitrios Pavlopoulos, Kunal Shrotri
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Publication number: 20200045083Abstract: A JIT service in a cloud computing environment manages just-in-time access to resources in the cloud computing environment for an external device. When JIT access to a resource is requested by a device, the JIT service retrieves a JIT policy for the resource that includes screening criteria limiting automatic granting of JIT access to users who meet the screening criteria. Screening information for a user associated with the request is evaluated against one or more screening requirements set forth by the screening criteria. If the screening criteria and any other criteria of the JIT policy are satisfied, the JIT service provisions JIT access to the resource for the device.Type: ApplicationFiled: October 14, 2019Publication date: February 6, 2020Inventors: RAMNATH PRASAD, PRADEEP AYYAPPAN NAIR, VEENA RAMACHANDRAN, SANDEEP KALARICKAL, THOMAS KNUDSON, PAVAN GOPAL BANDLA, CHETAN SHANKAR, RANAJOY SANYAL, QINGSU WU, CHI ZHOU, DOUG KIRSCHNER, RYAN MEYER, THOMAS KEANE
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Publication number: 20190371815Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material.Type: ApplicationFiled: June 11, 2019Publication date: December 5, 2019Applicant: Micron Technology, Inc.Inventors: Zhiqiang Xie, Chris M. Carlson, Justin B. Dorhout, Anish A. Khandekar, Greg Light, Ryan Meyer, Kunal R. Parekh, Dimitrios Pavlopoulos, Kunal Shrotri