Patents by Inventor RYAN P. KING

RYAN P. KING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Simulating a single data rate (SDR) mode on a dual data rate (DDR) memory controller for calibrating DDR memory coarse alignment
    Patent number: 10580476
    Abstract: A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ryan P. King, Stephen Glancy, John S. Bialas, Jr.
  • SIMULATING A SINGLE DATA RATE (SDR) MODE ON A DUAL DATA RATE (DDR) MEMORY CONTROLLER FOR CALIBRATING DDR MEMORY COARSE ALIGNMENT
    Publication number: 20190214073
    Abstract: A double data rate (DDR) memory controller writes a test pattern to a location in a DDR memory for a coarse calibration test, delayed by a first number of cycles set in a tunable write delay setting. The DDR memory controller simulates a single data rate (SDR) mode for the coarse calibration test by only comparing every other read beat of the test pattern read from the DDR memory, delayed by a second number of cycles set in tunable read delay setting, wherein every other read beat is latched for a full cycle. The DDR memory controller, responsive to every other read beat of the test pattern matching an expected result, sets the first number of cycles and the second number of cycles as coarse calibration settings for a DRAM.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: RYAN P. KING, STEPHEN GLANCY, JOHN S. BIALAS, JR.