Abstract: A hardware-based electronic trading system is disclosed that minimizes external memory accesses, thereby reducing overall latency. Order data for all open orders of a particular symbol, side, and price may be organized into a defined data structure, or tile, that can be fetched from an external memory cache. Once loaded into an internal memory cache of an FPGA or other fixed logic, the tile may be accessed often with minimal delay to obtain order data for multiple open orders having the same symbol, side, and price. To further minimize the number of external memory accesses, external memory can be provisioned as an asymmetric, multi-level memory cache that is tailored for handling large data sets of matching engine books and ticker plant services. In particular, the multi-level memory cache can be implemented using external memory units in the form of DRAMs for storing tiles according to a price priority scheme.

Abstract: Systems and methods are provided herein for efficient data relocation within a multi-level memory cache. In particular, the method can include (i) storing specific data structures, or tiles, in a first memory cache that contain open order data representing open orders for one of buying or selling a financial instrument at consecutive price levels that fall within a defined price range between a most aggressive price and a least aggressive price; (ii) storing multiple tiles in a second memory cache that contain open order data representing open orders for one of buying or selling the financial instrument at prices that fall outside the defined price range; and relocating tiles between the first memory cache and the second memory cache in response to changes in the open order data for one of buying or selling the financial instrument at the most aggressive price.