Abstract: A storage device and a data access method are provided. The storage device includes a primary storage unit and at least one additional unit. The primary storage unit includes: a primary memory element configured to store secret data and a primary access unit configured to receive an external access command. Each additional unit is configured to receive the external access command. Each additional unit includes: an additional memory element configured to store non-specific data, a local access generation element configured to trigger generating an internal access command based on the external access command, and an additional access unit configured to receive a local access command. The primary storage unit and each additional unit are coupled to a same power rail and a connection wire to simultaneously receive the external access command to parallelly (simultaneously) access the secret data and the non-specific data stored in each additional unit.

Abstract: A Real-Time Clock (RTC) block configured to output a current time as part of an ASIC configuration that guarantees that the RTC can never be rolled back beyond a checkpointed date and time. A checkpoint memory block is coupled to the RTC block and configured to include a stored active date/time checkpoint, and a set RTC logic block is coupled to the checkpoint memory block and to the RTC block and configured to permit setting the RTC block to an asserted new time request only when the asserted new time is in the future relative to the stored active date/time checkpoint. The active date/time checkpoint is stored in a non-volatile, single-write memory location such as in a one-time programmable (OTP) memory or in a bank of fuses so that the stored active date/time checkpoint is maintained whether or not power is interrupted to the checkpoint memory block.

Abstract: A Real-Time Clock (RTC) block configured to output a current time as part of an ASIC configuration that guarantees that the RTC can never be rolled back beyond a checkpointed date and time. A checkpoint memory block is coupled to the RTC block and configured to include a stored active date/time checkpoint, and a set RTC logic block is coupled to the checkpoint memory block and to the RTC block and configured to permit setting the RTC block to an asserted new time request only when the asserted new time is in the future relative to the stored active date/time checkpoint. The active date/time checkpoint is stored in a non-volatile, single-write memory location such as in a one-time programmable (OTP) memory or in a bank of fuses so that the stored active date/time checkpoint is maintained whether or not power is interrupted to the checkpoint memory block.

Abstract: A memory data scrambling system that can dynamically rescramble the contents of a memory while the system is in operation includes an application-specific integrated circuit (ASIC) that has an ASIC bus fabric, a double data rate (DDR) memory controller coupled to the ASIC bus fabric, a dynamic memory scrambler coupled to the DDR memory controller, the dynamic memory scrambler comprising a scrambler, a descrambler, a scrambler selection table, and a key generator and a DDR PHY coupled to the dynamic memory scrambler. The DDR PHY is coupled to an external DDR memory external to the ASIC. The dynamic memory scrambler includes a refresh timer that, upon expiration, causes data in a region of the DDR to be read, descrambled, rescrambled using a different scrambling key, and stored back into the region of the DDR in place of a DDR refresh.

Abstract: A memory data scrambling system that can dynamically rescramble the contents of a memory while the system is in operation includes an application-specific integrated circuit (ASIC) that has an ASIC bus fabric, a double data rate (DDR) memory controller coupled to the ASIC bus fabric, a dynamic memory scrambler coupled to the DDR memory controller, the dynamic memory scrambler comprising a scrambler, a descrambler, a scrambler selection table, and a key generator and a DDR PHY coupled to the dynamic memory scrambler. The DDR PHY is coupled to an external DDR memory external to the ASIC. The dynamic memory scrambler includes a refresh timer that, upon expiration, causes data in a region of the DDR to be read, descrambled, rescrambled using a different scrambling key, and stored back into the region of the DDR in place of a DDR refresh.

Abstract: Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware. In one implementation, a processing architecture includes a main processor configured to execute a first portion of a driver software to perform protocol control and management task associated with control or management packets in a packet-based protocol according to which packets are received from a device, an offload processor configured to execute a second portion of the driver software to perform data processing task for data packets received according to the packet-based protocol, an interface to enable communication with the device, and an interconnect coupled to the main processor, to the offload subsystem, and to the interface.

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Abstract: Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware. In one implementation, a processing architecture includes a main processor configured to execute a first portion of a driver software to perform protocol control and management task associated with control or management packets in a packet-based protocol according to which packets are received from a device, an offload processor configured to execute a second portion of the driver software to perform data processing task for data packets received according to the packet-based protocol, an interface to enable communication with the device, and an interconnect coupled to the main processor, to the offload subsystem, and to the interface.

Abstract: Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware.

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Abstract: Communication traffic processing architectures and methods are disclosed. Processing load on main Central Processing Units (CPUs) can be alleviated by offloading data processing tasks to separate hardware.

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Abstract: A high speed multi-lane serial interface and method for constructing frames for such an interface are provided. Frames are constructed for transmission on a multi-lane serial interface. For each of a plurality of transmit channels, packets are fragmented into fragments. Meta-frames are generated having a size defined by a constant meta-frame length×number of lanes, each frame having a meta-frame separator and a payload. Per-transmit channel flow control information is received. Each payload has a plurality of bursts, each burst comprising a burst control word and an associated data burst, the burst control word identifying one of said transmit channels to be transmitted on the associated data burst, each data burst comprising one of the fragments for the transmit channel identified in the associated burst control word. The channels to transmit in a given meta-frame are selected as a function of the received flow control information.

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Abstract: Apparatus and techniques relating to data interface power consumption control are disclosed. Components of a data transfer module may be selectively moved between their normal operating states and reduced power states at times when the data transfer module is not to be used for transferring data. Decisions as to particular components that are to be moved to their reduced power states may be based on respective timing characteristics of the components and/or respective power consumption characteristics of the components, for example. In some embodiments, an action may be performed to reduce a powering up time of the data transfer module when normal operation of the data transfer module is to resume. In the case of a multiple-connection interface having respective data transfer modules for each connection, the interface may be partially shut down by moving a subset of the data transfer modules into reduced power states.

Abstract: A high speed multi-lane serial interface and method for constructing frames for such an interface are provided. Frames are constructed for transmission on a multi-lane serial interface. For each of a plurality of transmit channels, packets are fragmented into fragments. Meta-frames are generated having a size defined by a constant meta-frame length×number of lanes, each frame having a meta-frame separator and a payload. Per-transmit channel flow control information is received. Each payload has a plurality of bursts, each burst comprising a burst control word and an associated data burst, the burst control word identifying one of said transmit channels to be transmitted on the associated data burst, each data burst comprising one of the fragments for the transmit channel identified in the associated burst control word. The channels to transmit in a given meta-frame are selected as a function of the received flow control information.

Abstract: A display system includes a light modulator divided into an array of individually controllable pixels and an input-driven illumination device. The illumination device is adapted to receive a variable input and is configured to direct light of variable intensity onto the modulator, depending on the input. The display system further includes a calibrating arrangement for establishing the input to the illumination device to produce a desired intensity level of light. The calibrating arrangement includes a light sensing mechanism, which senses the light from the illumination device while the illumination device is driven by an initial input. The calibration arrangement is configured to determine a comparison between the sensed light and a value representative of the desired-intensity level. The calibration arrangement further includes a control arrangement responsive to the comparison for varying the input so as to provide light of the desired intensity level.