Abstract: Capacitors that include an amorphous insulator layer can provide high capacitance density and low leakage. A capacitor may include two metal plates, a crystalline insulator material between the metal plates, and a thin layer of an amorphous insulator within the crystalline layer. The crystalline insulator material may be crystalline titanium dioxide, such as rutile, or a dielectric perovskite oxide, such as strontium titanium oxide or barium titanium oxide. The amorphous layer may be an amorphous oxide, such as amorphous titanium oxide, or a different oxide from the crystalline layer. The amorphous oxide layer may be sandwiched between two layers of the crystalline insulator. Alternatively, the amorphous oxide layer may be adjacent to one of the metal plates. The capacitors may be used in decoupling capacitors, memory, or for other applications.

Abstract: Disclosed herein are integrated circuit (IC) structures fabricated with techniques to reduce a gated subfin region in nanoribbon-based transistors. In one example, the technique involves depositing a film over the shallow trench insulator (STI) between adjacent subfins, where the film has a different material composition than the STI. In accordance with examples described herein, the film over the STI can protect the STI during various etch and clean processes to minimize unintentional recession of the STI and thus minimize the presence of gated subfins in the final IC structure. In some examples, the film may be present over the STI in the final IC structure in a plane with source or drain contact structures, and may also be present over the STI in a metal gate region.

Abstract: Integrated circuit (IC) device isolation structures between transistor gates. An IC device may include an electrically insulating structure between metal gates of adjacent transistors, and the insulating structure may include a dielectric liner around a different dielectric fill material and on sidewalls of the adjacent metal gates. The dielectric liner may be much thinner than the dielectric fill material. A metal via may be through, and in contact with, the dielectric fill material. The adjacent transistors and metal gates may be between frontside and backside interconnect structures, and the metal via may extend between, and couple, the interconnect structures.

Abstract: In a metallization layer of an integrated circuit device, air gaps are formed between adjacent metal lines, e.g., between high aspect ratio metal lines at tight pitches, to reduce the capacitance between the metal lines. A deposition process for a dielectric material between metal lines is tuned so that air gaps are formed within the dielectric material, in areas between metal lines. The dielectric material is also deposited between the upper portions of the metal lines, closing the air gaps from the top. The dielectric material is highly selective to a subsequent via etch, so that the dielectric material near the tops of the metal lines acts as an etch stop and prevents punch through into the air gaps.

Abstract: Integrated circuit structures having metal gate cut plug structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure includes silicon and oxygen, with oxygen in direct contact with a metal-containing layer of the gate electrode.

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having an improved liner structure to prevent oxidation of the gate electrode. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut includes a silicon nitride dielectric liner with a higher percentage of Si—H bonds compared to Si—N bonds at an interface between the dielectric liner and the gate structure. The liner may also include a higher percentage of Si—N bonds compared to Si—H bonds at an interface between the dielectric liner and a dielectric fill on the dielectric liner.

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

Abstract: Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N2:NH3 plasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N2:NH3 plasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps.

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

Abstract: Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate layer between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices.

Abstract: Transistors structures comprising a semiconductor features and dielectric material comprising silicon and oxygen in gaps or spaces between the features. The dielectric material may fill the gaps from bottom-up with an atomic layer deposition (ALD) process that includes a silicon deposition phase, and an oxidation phase augmented by N2:NH3 plasma activated nitrogen species. Being plasma activated, the nitrogen species have short mean free paths, and therefore preferentially passivate surfaces with low aspect ratios. This aspect-ratio dependent passivation may increase an energy barrier to surface reactions with a silicon precursor, resulting in a concomitant differential in deposition rate. With N2:NH3 plasma passivation, deposited dielectric material may have a nitrogen concentration that varies by at least order of magnitude as a function of the aspect ratio of the filled gaps.

Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

Abstract: An integrated circuit device includes: a semiconductor structure having a high aspect ratio (HAR) feature, the HAR feature having a depth of between 25 nanometers (nm) and 250 nm, a width of between 5 nm and 50 nm, and a depth-to-width aspect ratio of 5:1 or more; and a gap-fill material at least partially filling the HAR feature, the gap-fill material including silicon and nitrogen and being substantially free of a seam located between opposing sides of the HAR feature. A semiconductor process platform includes a nitrogen radical generator to generate nitrogen radicals for delivery to one of the zones, each zone being configured to deliver a separate precursor of a deposition cycle. A method of semiconductor device fabrication includes reacting surfaces of the HAR feature with a silicon precursor, and reacting the silicon-precursed surfaces with nitrogen plasma to form a monolayer of silicon nitride.

Abstract: An embodiment includes a dielectric material; a trench included in the dielectric material, the trench having first and second opposing sidewalls; wherein the trench includes: (a)(i) a first trench portion extending from the first sidewall to the second sidewall, (a)(ii) a second trench portion extending from the first sidewall to the second sidewall, and (a)(iii) a third trench portion extending from the first sidewall to the second sidewall; wherein the second trench portion is between the first trench portion and the third trench portion; wherein the first trench portion is substantially filled with a first material, the second trench portion is substantially filled with a second material, and the third trench portion is substantially filled with a third material; wherein (b)(i) the first material includes nitrogen, and (b)(ii) the first material includes more nitrogen than the third material. Other embodiments are described herein.

Abstract: An embodiment includes a dielectric material; a trench included in the dielectric material, the trench having first and second opposing sidewalls; wherein the trench includes: (a)(i) a first trench portion extending from the first sidewall to the second sidewall, (a)(ii) a second trench portion extending from the first sidewall to the second sidewall, and (a)(iii) a third trench portion extending from the first sidewall to the second sidewall; wherein the second trench portion is between the first trench portion and the third trench portion; wherein the first trench portion is substantially filled with a first material, the second trench portion is substantially filled with a second material, and the third trench portion is substantially filled with a third material; wherein (b)(i) the first material includes nitrogen, and (b)(ii) the first material includes more nitrogen than the third material. Other embodiments are described herein.