Abstract: Technologies for compilers that implement non-power of two Fast Fourier Transform (FFT) algorithms are described. The non-power of two FFT algorithm uses a recursive function to generate a hardware design of a set of compute blocks of a fixed-point digital signal processor (DSP) and routing data between the compute blocks. The compiler receives input specifying a sequence of indexes and a bit width of the fixed-point DSP and performs a process. The process splits the sequence using a recursive loop, determines a number of multiplications in the hardware design, and generates a trace graph of the non-power of two FFT algorithm. The process is entered via the recursive function and exists when the recursive loop decrements to a specified value corresponding to a Radix-3 or Radix-2. The compiler outputs data, including the hardware design, the number of multiplications in the hardware design, and the trace graph.

Abstract: Technologies directed to carrier frequency offset (CFO) compensation is described. An input buffer receives a first set of incoming samples associated with a first frequency from an incoming data stream. A first outgoing sample of an outgoing data stream is generated using the first set of incoming samples. The first outgoing sample is associated with a second frequency. A ratio between the first and second frequencies is used to determine that the first outgoing sample is associated with a misalignment between the incoming data stream and the outgoing data stream. The input buffer receives a second set of incoming samples associated with the first frequency from the incoming data stream. A second outgoing sample of the outgoing data stream is generated using the second set of incoming samples. The second outgoing sample is associated with the second frequency. The first outgoing sample is overwritten by the second outgoing sample.

Abstract: Various examples are directed to isolated analog-to-digital converter (ADC) circuits comprising a first side that is separated from a second side by an isolator. A first ADC positioned on the first side may be configured to convert a first analog input signal to a first side multi-bit digital signal. A digital modulator on the first side may be configured to convert the first side multi-bit digital signal to a first single-bit stream. A first filter positioned on the second side may be configured to receive the first single-bit stream across the first isolator and to generate a first reconstructed multi-bit digital signal using the first single-bit stream.

Abstract: Various examples are directed to isolated analog-to-digital converter (ADC) circuits comprising a first side that is separated from a second side by an isolator. A first ADC positioned on the first side may be configured to convert a first analog input signal to a first side multi-bit digital signal. A digital modulator on the first side may be configured to convert the first side multi-bit digital signal to a first single-bit stream. A first filter positioned on the second side may be configured to receive the first single-bit stream across the first isolator and to generate a first reconstructed multi-bit digital signal using the first single -bit stream.