Patents by Inventor Ryan Rakvic
Ryan Rakvic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8839258Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.Type: GrantFiled: January 20, 2012Date of Patent: September 16, 2014Assignee: Intel CorporationInventors: Ryan Rakvic, Richard A. Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K. Poulsen, Sanjiv Shah, John Shen, Gautham Chinya
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Publication number: 20120131366Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.Type: ApplicationFiled: January 20, 2012Publication date: May 24, 2012Inventors: Ryan Rakvic, Richard A. Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K. Poulsen, Sanjiv Shah, John Shen, Gautham Chinya
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Patent number: 8108863Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.Type: GrantFiled: December 30, 2005Date of Patent: January 31, 2012Assignee: Intel CorporationInventors: Ryan Rakvic, Richard A. Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David K. Poulsen, Sanjiv Shah, John Shen, Gautham Chinya
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Patent number: 7665000Abstract: An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.Type: GrantFiled: March 7, 2007Date of Patent: February 16, 2010Assignee: Intel CorporationInventors: Antonio Gonzalez, Qiong Cai, Jose Gonzalez, Pedro Chaparro, Grigorios Magklis, Ryan Rakvic
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Publication number: 20080222466Abstract: An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.Type: ApplicationFiled: March 7, 2007Publication date: September 11, 2008Inventors: Antonio Gonzalez, Qiong Cai, Jose Gonzalez, Pedro Chaparro, Grigorios Magklis, Ryan Rakvic
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Publication number: 20070157206Abstract: A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Inventors: Ryan Rakvic, Richard Hankins, Ed Grochowski, Hong Wang, Murali Annavaram, David Poulsen, Sanjiv Shah, John Shen, Gautham Chinya
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Publication number: 20070124732Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may receive compiler-generated hints from a compiler. The compiler hints may be generated by the compiler without user-provided pragmas, and may be passed to the scheduler routine via an API-like interface. The interface may include a scheduling hint data structure that is maintained by the compiler. Other embodiments are also described and claimed.Type: ApplicationFiled: November 29, 2005Publication date: May 31, 2007Inventors: Shih-wei Lia, Ryan Rakvic, Richard Hankins, Hong Wang, Gansha Wu, Guei-Yuan Lueh, Xinmin Tian, Paul Petersen, Sanjiv Shah, Trung Diep, John Shen, Gautham Chinya
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Publication number: 20070074217Abstract: Method, apparatus and system embodiments to schedule user-level OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine resides in user space and may be part of a runtime library. The library may also include monitoring logic that monitors execution of a shredded program and provides scheduling hints, based on shred dependence information, to the scheduler. In addition, the scheduler may further optimize shred scheduling by taking into account information about a system's configuration of thread execution hardware. Other embodiments are also described and claimed.Type: ApplicationFiled: September 26, 2005Publication date: March 29, 2007Inventors: Ryan Rakvic, Richard Hankins, Hong Wang, Trung Diep, Xinmin Tain, Paul Petersen, Sanjiv Shah, John Shen, Gautham Chinya, Shivnandan Kaushik, Bryant Bigbee, Baiju Patel, Douglas Armstrong
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Publication number: 20060282839Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.Type: ApplicationFiled: June 13, 2005Publication date: December 14, 2006Inventors: Richard Hankins, Gautham Chinya, Hong Wang, Shivnandan Kaushik, Bryant Bigbee, John Shen, Trung Diep, Xiang Zou, Baiju Patel, Paul Petersen, Sanjiv Shah, Ryan Rakvic, Prashant Sethi
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Patent number: 7120749Abstract: According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.Type: GrantFiled: March 18, 2004Date of Patent: October 10, 2006Assignee: Intel CorporationInventors: Ryan Rakvic, Youfeng Wu, Bryan Black, John Shen
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Publication number: 20060224858Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.Type: ApplicationFiled: April 5, 2005Publication date: October 5, 2006Inventors: Hong Wang, Gautham Chinya, Richard Hankins, Shivnandan Kaushik, Bryant Bigbee, Per Hammarlund, Xiang Zou, Jason Brandt, Prashant Sethi, Douglas Carmean, Baiju Patel, John Shen, Scott Rodgers, Ryan Rakvic, John Reid, David Poulsen, Sanjiv Shah, James Held, James Abel
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Publication number: 20060117141Abstract: Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.Type: ApplicationFiled: January 9, 2006Publication date: June 1, 2006Inventors: Ryan Rakvic, John Shen, Deepak Limaye
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Patent number: 6954848Abstract: After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.Type: GrantFiled: January 2, 2002Date of Patent: October 11, 2005Assignee: Intel CorporationInventors: Ryan Rakvic, Christopher Wilkerson, Bryan Black, Edward Grochowski, John Shen, Edward Brekelbaum
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Publication number: 20050210197Abstract: According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.Type: ApplicationFiled: March 18, 2004Publication date: September 22, 2005Inventors: Ryan Rakvic, Youfeng Wu, Bryan Black, John Shen
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Publication number: 20030126412Abstract: After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is read in a next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.Type: ApplicationFiled: January 2, 2002Publication date: July 3, 2003Inventors: Ryan Rakvic, Christopher Wilkerson, Bryan Black, Edward Grochowski, John Shen, Edward Brekelbaum