Patents by Inventor Ryan Sheil

Ryan Sheil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250003061
    Abstract: Exemplary processing methods may include providing a component for semiconductor processing to a processing region of a processing chamber. The methods may include providing one or more interface deposition precursors to the processing region. The methods may include depositing a layer of interface material on the component for semiconductor processing in the processing region. The methods may include providing one or more coating deposition precursors to the processing region. The methods may include depositing a layer of coating material on the component for semiconductor processing in the processing region.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Nitin Deepak, Ryan Sheil, Katherine Woo, Juan Carlos Rocha-Alvarez, Jennifer Y. Sun
  • Publication number: 20240429065
    Abstract: A method of manufacturing an interconnect in a metal layer in a back-end-of-line of a semiconductor device includes N2 plasma passivation, through an opening a hard mask, of a ruthenium layer on a substrate. The N2 plasma passivation forms a ruthenium nitride layer on the ruthenium layer. The ruthenium nitride layer includes a first portion aligned with the opening and a second portion underneath the hard mask. The method also includes H2 plasma reduction of the ruthenium nitride layer after the N2 plasma passivation. The H2 plasma reduction removes the first portion of the ruthenium nitride layer. The method also includes O2 plasma etching the ruthenium layer after the H2 plasma reduction. The method also includes repeatedly performing the N2 plasma passivation, the H2 plasma reduction, and the O2 plasma etching to remove the ruthenium layer down to the substrate.
    Type: Application
    Filed: June 18, 2024
    Publication date: December 26, 2024
    Inventors: Jane P. Chang, Owen Watkins, Harsono S. Simka, Ryan Sheil
  • Publication number: 20240347336
    Abstract: Exemplary processing methods may include providing a component for semiconductor processing to a processing region of a processing chamber. The methods may include providing one or more deposition precursors to the processing region. The one or more deposition precursors may include a metal-containing precursor and a fluorine-containing precursor. The methods may include depositing a layer of material on the component for semiconductor processing in the processing region. The layer of material comprises a metal-and-fluorine-containing material.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Nitin Deepak, Ryan Sheil, Jennifer Y. Sun, Zhijun Jiang, Katherine Woo
  • Publication number: 20240327300
    Abstract: Exemplary processing methods may include providing a powder to a processing region of a processing chamber. The methods may include providing one or more deposition precursors to the processing region. The methods may include generating plasma effluents of the one or more deposition precursors. The methods may include depositing a layer of material on the powder in the processing region. The layer of material may include a corrosion-resistant material. A temperature within the processing chamber is maintained at less than or about 700° C.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Nitin Deepak, Katherine Woo, Ryan Sheil, Juan Carlos Rocha-Alvarez, Jennifer Y. Sun
  • Publication number: 20240153745
    Abstract: Semiconductor fabrication component preparation methods are described. In embodiments, the methods include forming a first layer on a surface of the semiconductor fabrication component. The first layer is characterized by a porosity of greater than or about 0.01 vol. %. The methods further include depositing a second layer on the first layer, where the second layer is characterized by a porosity of less than or about 20 vol. %. Treated semiconductor fabrication components are also described. In embodiments, the treated components include a first layer formed in the surface of the semiconductor fabrication component, where the first layer is characterized by a porosity of greater than or about 0.01 vol. %., and a second layer positioned on the first layer, where the second layer is characterized by a porosity of less than or about 20 vol. %.
    Type: Application
    Filed: November 5, 2022
    Publication date: May 9, 2024
    Inventors: Katherine Woo, Jennifer Y. Sun, Jian Li, Wenhao Zhang, Mayur Govind Kulkarni, Chidambara A. Ramalingam, Ryan Sheil, Martin J. Seamons, Nitin Deepak