Abstract: A method includes receiving, using a processing device, a first condition associated with an operation at a data center, where the operation at the data center pertains to a first location at the data center, the first location corresponding to a first parameter value. The method further includes providing the first condition as an input to a machine learning model. The method also includes performing one or more reinforcement learning techniques using the machine learning model to cause the machine learning model to output an indication of a final location associated with the operation, where the final location corresponds to a final parameter value that is closer to a target than the first parameter value corresponding to the first location at the data center.

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.

Abstract: The present disclosure pertains to compositions and methods for the treatment and/or prevention of one or more of obesity, diabetes, metabolic syndrome, Alzheimer's disease, Chronic Fatigue Syndrome (CFS), aging, fibromyalgia, dyslipidemia, hypercholesterolemia, dyslipidemia, Parkinson's disease, migraines, Traumatic Brain Injury (TBI), Attention Deficit Disorder (ADD)/Attention Deficit Hyperactivity Disorder (ADHD), Cancer, Cardiovascular Disease (CVD)/Coronary Artery Disease (CAD), Chronic Pain, neuralgia, depression, amyotrophic lateral sclerosis (ALS), and epilepsy, Insufficient Cellular Energy (ICE) and mitochondrial dysfunction. The present disclosure also pertains to methods for increasing mental and/or physical performance levels and/or decreasing exertion during exercise in a subject by the administration of C5 ketones.

Abstract: A vehicle interface control unit for a vehicle comprises an accessories module to detect an accessory fitted to the vehicle an input module to receive one or more input signals from a vehicle electronic control unit, ECU; and a display control module to determine a display setting of an interface element for control of the detected accessory based on the received input signals, and control a display unit to show the interface element according to the determination.

Abstract: Systems and methods are provided herein to improve control of automatic driver assist systems in a vehicle and a vehicle comprising said systems, for example, by enabling the automatic driver assist systems to be selectively deactivated or activated under certain conditions.

Abstract: Systems are provided for a crankcase ventilation system. In one example, a crankcase ventilation (CCV) system for an engine configured to transmit crankcase gases into a clean side air duct, the clean side air duct comprising a sensor and a crankcase ventilation spigot, wherein the crankcase ventilation spigot is configured to be disposed downstream of the sensor, the crankcase ventilation spigot having an outlet configured to direct crankcase gases emerging from the crankcase ventilation spigot away from the sensor.

Abstract: Systems are provided for a crankcase ventilation system. In one example, a crankcase ventilation (CCV) system for an engine configured to transmit crankcase gases into a clean side air duct, the clean side air duct comprising a sensor and a crankcase ventilation spigot, wherein the crankcase ventilation spigot is configured to be disposed downstream of the sensor, the crankcase ventilation spigot having an outlet configured to direct crankcase gases emerging from the crankcase ventilation spigot away from the sensor.

Abstract: Systems are provided for a crankcase ventilation system. In one example, a crankcase ventilation (CCV) system for an engine configured to transmit crankcase gases into a clean side air duct, the clean side air duct comprising a sensor and a crankcase ventilation spigot, wherein the crankcase ventilation spigot is configured to be disposed downstream of the sensor, the crankcase ventilation spigot having an outlet configured to direct crankcase gases emerging from the crankcase ventilation spigot away from the sensor.

Abstract: Systems are provided for a crankcase ventilation duct. In one example, the crankcase ventilation duct is integrally formed with a compressor housing wherein surfaces of the compressor housing shape a passage of the crankcase ventilation duct.

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

Abstract: In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.