Patents by Inventor Ryan Yamase

Ryan Yamase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Silicon nitride passivation layer for covering high aspect ratio features
    Patent number: 8563095
    Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: October 22, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Ryan Yamase, Ji Ae Park, Shamik Patel, Thomas Nowak, Zhengjiang “David” Cui, Mehul Naik, Heung Lak Park, Ran Ding, Bok Hoen Kim
  • Fabrication of through-silicon vias on silicon wafers
    Patent number: 8329575
    Abstract: A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 11, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
  • Fabrication of through-silicon vias on silicon wafers
    Patent number: 8283237
    Abstract: A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: October 9, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
  • FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS
    Publication number: 20120164829
    Abstract: A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nagarajan Rajagopalan, Ji Ae Park, Ryan Yamase, Shamik Patel, Thomas Nowak, Li-Qun Xia, Bok Hoen Kim, Ran Ding, Jim Baldino, Mehul Naik, Sesh Ramaswami
  • FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS
    Publication number: 20120164827
    Abstract: A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nagarajan RAJAGOPALAN, Ji Ae PARK, Ryan YAMASE, Shamik PATEL, Thomas NOWAK, Li-Qun XIA, Bok Hoen KIM, Ran DING, Jim BALDINO, Mehul NAIK, Sesh RAMASWAMI
  • SILICON NITRIDE PASSIVATION LAYER FOR COVERING HIGH ASPECT RATIO FEATURES
    Publication number: 20110223765
    Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 15, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nagarajan RAJAGOPALAN, Xinhai HAN, Ryan YAMASE, Ji Ae PARK, Shamik PATEL, Thomas NOWAK, Zhengjiang "David" CUI, Mehul NAIK, Heung Lak PARK, Ran DING, Bok Hoen KIM