Abstract: A directional coupler includes a main line through which a signal is transmitted, first and second sub-lines that are selectively coupled to the main line, and a common output port that outputs a detection signal generated by the signal transmitted through the main line, wherein a first degree of coupling between the main line and the first sub-line is different than a second degree of coupling between the main line and the second sub-line.

Abstract: A directional coupler includes a main line, a first sub-line to be electromagnetically coupled to the main line, a second sub-line to be electromagnetically coupled to the main line, and a coupling terminal configured to output a detection signal corresponding to a radio frequency signal that is transmitted through the main line, the first sub-line and the second sub-line are different in length from each other, and connection between the first sub-line and the coupling terminal and connection between the second sub-line and the coupling terminal are switched.

Abstract: A directional coupler (2) includes a main line (11), a sub-line (12), a variable terminator (13), and a variable filter circuit (15). The variable terminator (13) is a variable impedance circuit that terminates one end portion of the sub-line (12). The variable filter circuit (15) is connected to the other end portion of the sub-line (12). The variable filter circuit (15) may include a filter, a bypass path, and a switch which is connected to at least one of the filter and the bypass path.

Abstract: A filter module includes a first ground terminal, a second ground terminal, a low pass filter, and a second inductor. The low pass filter includes a first inductor provided in an input/output path of signal, a first capacitor provided in a first path connecting a first node and the first ground terminal, and a second capacitor provided in a second path connecting a second node and the second ground terminal. The second inductor is connected in series to the second capacitor in a path connecting the second capacitor and the second ground terminal. The first path and the second path are not connected to each other by any path except the one between the first node and the second node.

Abstract: A dielectric having a first main surface and a second main surface facing each other, a main line provided on a side of the first main surface in contact with the dielectric, and a sub line provided on the side of the first main surface in contact with the dielectric are included, the dielectric has a first portion in contact with the main line and a second portion in contact with the sub line, and when the first main surface is viewed in a plan view, between the first portion and the second portion, a third portion having a relative dielectric constant changing along a direction intersecting with the main line and the sub line is located.

Abstract: A directional coupler includes a main line for transmitting a high frequency signal, a sub line electromagnetically coupled to the main line, a termination circuit for terminating one end portion of the sub line, and a variable filter that has an input terminal and an output terminal and the input terminal is connected to another end portion of the sub line. The variable filter is a filter unit circuit having one frequency band as a pass band or a stop band, and in the filter unit circuit, a variable passive element for shifting a frequency in the pass band or the stop band is disposed.

Abstract: Bidirectional detection is performed with a suppressed increase in return loss at an output terminal. A bidirectional coupler includes a detection port, a main line connected to a first port and a second port, a sub-line, a termination circuit, a switch circuit that switches each of one end and another end of the sub-line to the termination circuit or the detection port, and a matching network disposed between the switch circuit and the detection port and including at least one of a first variable capacitor, a first variable inductor, or a first variable resistor. In a first mode for detecting a first signal, the switch circuit connects the one end of the sub-line to the detection port, and connects the other end of the sub-line to the termination circuit.

Abstract: A bidirectional coupler includes: a multilayer substrate; and a first main line, a second main line, and a sub line which are provided in or on the multilayer substrate. The sub line includes a first line portion being a portion electromagnetically coupled with the first main line and an even number of second line portions being portions electromagnetically coupled with the second main line. One half of the second line portions is provided between the first line portion and one end portion of the sub line, and the other half of the second line portions is provided between the first line portion and the other end portion of the sub line.

Abstract: A bidirectional coupler includes a multilayer board, a first main line, a second main line, a third main line, and an sub line. The sub line includes a first line portion, an even number of second line portions, and an even number of third line portions. One half of the second line portions is provided between the first line portion and one end of the sub line. The other half of the second line portions is provided between the first line portion and the other end of the sub line. One half of the third line portions is provided between the one half of the second line portions and the one end of the sub line. The other half of the third line portions is provided between the other half of the second line portions and the other end of the sub line.

Abstract: A bidirectional coupler includes a multilayer board, a first main line, a second main line, a third main line, and an sub line. The sub line includes a first line portion, an even number of second line portions, and an even number of third line portions. One half of the second line portions is provided between the first line portion and one end of the sub line. The other half of the second line portions is provided between the first line portion and the other end of the sub line. One half of the third line portions is provided between the one half of the second line portions and the one end of the sub line. The other half of the third line portions is provided between the other half of the second line portions and the other end of the sub line.

Abstract: A bidirectional coupler includes: a multilayer substrate; and a first main line, a second main line, and a sub line which are provided in or on the multilayer substrate. The sub line includes a first line portion being a portion electromagnetically coupled with the first main line and an even number of second line portions being portions electromagnetically coupled with the second main line. One half of the second line portions is provided between the first line portion and one end portion of the sub line, and the other half of the second line portions is provided between the first line portion and the other end portion of the sub line.

Abstract: A bidirectional coupler includes the following elements. A main line and a sub-line are electromagnetically coupled. First and second resistors are each grounded at one end. First and second switches connect the sub-line to the first and second resistors or a third port. A third resistor is disposed between one end of the sub-line and the first switch or between the other end of the sub-line and the second switch. When detecting an input signal, the first switch electrically connects one end of the sub-line to the other end of the first resistor and the second switch electrically connects the other end of the sub-line to the third port. When detecting a reflected signal, the first switch electrically connects one end of the sub-line to the third port and the second switch electrically connects the other end of the sub-line to the other end of the second resistor.

Abstract: A power-on reset circuit includes a first resistor having one end connected to a power source node; a first capacitor connected to another end of the first resistor; a second resistor having one end connected to the power source node; a second capacitor connected to another end of the second resistor; a first inverter having a power source terminal connected to the other end of the first resistor and an input terminal connected to the other end of the second resistor; and a second inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to an output terminal of the first inverter, and an output terminal electrically connected to a reset signal output terminal.

Abstract: An amplifier includes a first FET having a first back-gate end, a second FET having a second back-gate end, a third FET having a third back-gate end, a first power supply terminal configured to apply a voltage to the first back-gate end, a second power supply terminal configured to apply a voltage to the second back-gate end, and a third power supply terminal configured to apply a voltage to the third back-gate end. In the stated amplifier, the first through third power supply terminals are configured such that different voltages can be set to the first through third power supply terminals.

Abstract: A semiconductor package includes the following elements. A high-output switch IC includes an IC top surface on which an electrode is disposed and an IC bottom surface on which no electrode is disposed. A connecting terminal is formed at a position outside a projection region toward a side portion of the semiconductor package. The projection region is a region projected in a thickness direction of the high-output switch IC. A wire electrically connects the electrode and the connecting terminal. A mold resin section covers the IC top surface and the wire and also covers a surface of the connecting terminal to which the wire is connected. A surface of the connecting terminal opposite to the surface to which the wire is connected is not covered with the mold resin section but is exposed. The IC bottom surface is not covered with a metal.

Abstract: A power-on reset circuit includes a first resistor having one end connected to a power source node; a first capacitor connected to another end of the first resistor; a second resistor having one end connected to the power source node; a second capacitor connected to another end of the second resistor; a first inverter having a power source terminal connected to the other end of the first resistor and an input terminal connected to the other end of the second resistor; and a second inverter having a power source terminal connected to the other end of the first resistor, an input terminal connected to an output terminal of the first inverter, and an output terminal electrically connected to a reset signal output terminal.

Abstract: An amplifier includes a first FET having a first back-gate end, a second FET having a second back-gate end, a third FET having a third back-gate end, a first power supply terminal configured to apply a voltage to the first back-gate end, a second power supply terminal configured to apply a voltage to the second back-gate end, and a third power supply terminal configured to apply a voltage to the third back-gate end. In the stated amplifier, the first through third power supply terminals are configured such that different voltages can be set to the first through third power supply terminals.

Abstract: A front end device includes an upper-level device and a lower-level device. The upper-level device includes an S/P interface unit. The lower-level device includes a parallel interface unit and a high-frequency processor. The S/P interface unit is connected to an RFIC and the parallel interface unit, receives a serial signal from the RFIC, converts the serial signal into a parallel signal, and transmits the parallel signal to the parallel interface unit. The parallel interface unit receives the parallel signal and supplies the parallel signal to the high-frequency processor. The high-frequency processor is connected between the RFIC and an antenna and performs certain processing on a high-frequency signal based on the parallel signal.

Abstract: A first envelope detector circuit and a second envelope detector circuit are the same in circuit configuration, where the former detects an input high frequency signal, and the latter generates a reference voltage for power level detection. A detector detects an output voltage of a selector configured to select an output of the first envelope detector circuit with reference to an output voltage of a selector configured to select an output of the second envelope detector circuit. A controller controls an input selector to determine and store control values for the two selectors during input of a high frequency reference signal generated by a high frequency reference signal generating unit, and controls the two selectors by using the stored control values when an actual high frequency signal is input.

Abstract: A front end device includes an upper-level device and a lower-level device. The upper-level device includes an S/P interface unit. The lower-level device includes a parallel interface unit and a high-frequency processor. The S/P interface unit is connected to an RFIC and the parallel interface unit, receives a serial signal from the RFIC, converts the serial signal into a parallel signal, and transmits the parallel signal to the parallel interface unit. The parallel interface unit receives the parallel signal and supplies the parallel signal to the high-frequency processor. The high-frequency processor is connected between the RFIC and an antenna and performs certain processing on a high-frequency signal based on the parallel signal.