Abstract: The present invention provides a novel copolymer available for a drug delivery technique. More particularly, a novel copolymer for a drug delivery carrier targeting a tumor is provided. The present invention relates to a copolymer comprising structural units represented by the following formulas (A), (B), and (C): wherein R1, R2, and R3 are the same or different and represent a hydrogen atom or a C1-3 alkyl group, R4 represents a C1-3 alkyl group, R5 represents a hydrogen atom, a C1-18 alkyl group, a 3- to 8-membered cycloalkyl group optionally having a substituent, an adamantyl group, a C6-18 aryl group optionally having a substituent, or a 5- to 10-membered heteroaryl group optionally having a substituent, X1, X2, and X3 are the same or different and represent an oxygen atom, a sulfur atom, or N—R7, R6 represents a hydrogen atom, a leaving group, or a linker, R7 represents a hydrogen atom or a C1-3 alkyl group, m represents an integer of 1 to 100, and n represents an integer of 0 to 3.

Abstract: The present invention provides curable calcium phosphate dental cement that has excellent sealability for dentinal tubule, is expected to form fluoroapatite, and has a curing time that is advantageous for clinical use. The present invention is directed to curable calcium phosphate dental cement including: a first material as powder or nonaqueous paste; and a second material as liquid or aqueous paste, and, in the curable calcium phosphate dental cement, the first material comprises tetracalcium phosphate (A), alkali metal salt of phosphoric acid (B), and acidic calcium phosphate (C), the second material comprises water (D), and at least one of the first material and the second material comprises a fluorine compound (E) and an organic acid (F) having a molecular weight of 10000 or less.

Abstract: Apparatuses, systems, and methods for a per-DRAM addressability (PDA) synchronizer circuit. The PDA synchronizer circuit receives a write command signal which may be synchronous to a DQS clock as part of a first PDA mode or asynchronous as part of a second PDA mode. The PDA synchronizer circuit includes a delay path which provides a first PDA signal responsive to the write command signal and a synchronizer which provides a second PDA signal responsive to the write command signal. The PDA synchronizer circuit provides a synchronized write command signal responsive to whichever of the first PDA signal or the second PDA signal was provided first. When a PDA mode is disabled, the write command signal may be passed as the synchronized write command signal.

Abstract: Apparatuses for timing control in a write path are disclosed. An example apparatus includes: a clock input circuit that receives a clock signal and provides an internal clock signal; a command decoder that receives command signals and the internal clock signal, and provides an active write command signal when the command signals indicates a write operation; a write latency shifter that receives the write command signal, a latency value and a WICA value, adjusts timing of the write command signal responsive to the latency value and the WICA value, and provides a shifted write command signal; and a write DLL including a delay line that receives the shifted write command signal and provides a delayed write command signal. The write DLL provides the WICA value to set a propagation time from the clock input circuit to the write DLL to be a multiple of a period of the clock signal.

Abstract: Apparatuses and methods for arranging read data for output are described. An example apparatus includes a clock circuit, a data output circuit, and a control circuit. The clock circuit is configured to provide multiphase clock signals having different phases from each other based on a clock signal. The data output circuit is configured to receive a plurality of read data bits responsive to a read command and serially output each of the plurality of read data bits in synchronism with a corresponding one of the multiphase clock signals. The control circuit is configured to determine the correspondences between the plurality of read data bits and the multiphase clock signals based on information about which of the multiphase clock signals captures the read command.

Abstract: Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.

Abstract: Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.

Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a read state circuit configured to control the schedule/timing associated with parallel pipelines, and (2) a timing control circuit configured to coordinate output of data from the parallel pipelines.

Abstract: Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.

Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a read state circuit configured to control the schedule/timing associated with parallel pipelines, and (2) a timing control circuit configured to coordinate output of data from the parallel pipelines.

Abstract: Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.

Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

Abstract: A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay elements as an output clock signal. The method includes resetting an initial delay control circuit, generating, with the initial delay control circuit, a pulse based on a period of an input clock signal, determining, with the initial delay control circuit, a number of delay elements required to produce a delay time at least substantially equivalent to a pulse width for a preset signal, initializing the counter circuit based on the preset signal and adjusting the counter circuit in response to phases of the input and output clock signals.

Abstract: A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay elements as an output clock signal. The method includes resetting an initial delay control circuit, generating, with the initial delay control circuit, a pulse based on a period of an input clock signal, determining, with the initial delay control circuit, a number of delay elements required to produce a delay time at least substantially equivalent to a pulse width for a preset signal, initializing the counter circuit based on the preset signal and adjusting the counter circuit in response to phases of the input and output clock signals.

Abstract: A semiconductor device includes a DLL circuit, which comprises: a delay unit generating a second clock signal by delaying a first clock signal; a phase comparator circuit comparing the first clock signal and a signal generated by further delaying the second clock signal; a counter circuit outputting a count value that determines a delay amount of the delay unit to the delay unit, and up/down operating in response to the result of the phase comparison by the phase comparator circuit; and an initial delay amount control circuit detecting a cycle of the first clock signal at the time of initial setting operation, and outputting an initial value of the count value depending upon the detected cycle to the counter circuit.

Abstract: A semiconductor device includes a DLL circuit, which comprises: a delay unit generating a second clock signal by delaying a first clock signal; a phase comparator circuit comparing the first clock signal and a signal generated by further delaying the second clock signal; a counter circuit outputting a count value that determines a delay amount of the delay unit to the delay unit, and up/down operating in response to the result of the phase comparison by the phase comparator circuit; and an initial delay amount control circuit detecting a cycle of the first clock signal at the time of initial setting operation, and outputting an initial value of the count value depending upon the detected cycle to the counter circuit.