Patents by Inventor Ryo Hattori
Ryo Hattori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040108556Abstract: A semiconductor device includes a semiconductor substrate having one principal plane on which a plurality of electrodes are formed. A film which is made of polymer with a low dielectric constant is formed over the gate and drain electrodes so as to insulate the gate and drain electrodes from the source electrode. A chip surface electrode is formed over the low-dielectric-constant polymer film and the source electrode, and connected to a ground potential. The source electrode is provided with a ground potential through the chip surface electrode.Type: ApplicationFiled: December 1, 2003Publication date: June 10, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Kunii, Ryo Hattori, Hiroshi Kawata
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Publication number: 20040029390Abstract: In a method for evaluating a semiconductor crystal substrate which includes a collector layer, a base layer, and an emitter layer and is used for a heterojunction bipolar transistor, a semiconductor crystal substrate to be evaluated which includes a crystal layer whose composition is the same as that of the base layer is produced. Excitation light is irradiated to the semiconductor crystal substrate to be evaluated and a change with time in an intensity of photoluminescence from the crystal layer is measured before the intensity becomes saturated. A change with time in a current gain of the heterojunction bipolar transistor produced using the semiconductor crystal substrate is measured based on the change with time in the intensity.Type: ApplicationFiled: January 21, 2003Publication date: February 12, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yoshitsugu Yamamoto, Satoshi Suzuki, Ryo Hattori
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Publication number: 20030198743Abstract: The present invention is to provide a silicon nitride film forming apparatus and a forming method which makes possible the high reproducibility of film quality or film thickness. The silicon nitride film forming apparatus and forming method in which a heating element and a substrate are arranged in a vacuum vessel connected to a gas exhaust system and a gas supply system to deposit a silicon nitride film on the substrate surface by maintaining the heating element at a predetermined temperature and by decomposing and/or activating a raw material gas supplied from the gas supply system, comprises: an inner wall which is arranged in the vacuum vessel surrounding the heating element and the substrate so as to form a film formation space, a gas introduction means to introduce the raw material gas to the film forming space, and at least one of a heating means and a cooling means of the inner wall arranged to control the inner wall to a predetermined temperature.Type: ApplicationFiled: April 22, 2003Publication date: October 23, 2003Inventors: Hitoshi Morisaki, Yasushi Kamiya, Shuji Nomura, Masahiro Totuka, Tomoki Oku, Ryo Hattori
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Publication number: 20030194881Abstract: A process of manufacturing a semiconductor device uses catalytic chemical vapor deposition process, and has three steps. In the process, a reaction chamber (10) including a catalyzer (6) and a substrate (1) therein is provided. Gases including silane gas, ammonia gas, and hydrogen gas are provided. The gases are supplied to the reaction chamber, the gases are brought into contact with the catalyzer, and then towards onto the substrate to deposit the silicon nitride film.Type: ApplicationFiled: October 21, 2002Publication date: October 16, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Masahiro Totsuka, Tomoki Oku, Ryo Hattori
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Patent number: 6570390Abstract: A method of measuring a surface leakage current includes applying a voltage between a pair of electrodes, which are apart from each other on a sample surface, during a predetermined period of time. A region of the sample surface between the pair of electrodes is irradiated by energy rays during an irradiation period of time which is within the voltage application time. The energy rays may be lasers, ultraviolet rays, X-rays or an electron beam. A current flowing between the pair of electrodes is measured during the voltage application time. The energy rays irradiation causes a surface leakage current, which is caused by adhered substances, to start to flow, and when the adhered substances have been eliminated perfectly, a relatively large current caused by the adhered substances disappears. Perfect elimination of the adhered substances can be verified by confirming that the relatively large current has disappeared.Type: GrantFiled: August 29, 2001Date of Patent: May 27, 2003Assignees: Rigaku Corporation, Mitsubishi Denki Kabushiki KaishaInventors: Taisei Hirayama, Koichiro Ito, Ryo Hattori, Yoshitsugu Yamamoto, Yoshihiro Notani, Shinichi Miyakuni
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Publication number: 20020030504Abstract: A method of measuring a surface leakage current includes applying a voltage between a pair of electrodes, which are apart from each other on a sample surface, during a predetermined period of time. A region of the sample surface between the pair of electrodes is irradiated by energy rays during an irradiation period of time which is within the voltage application time. The energy rays may be lasers, ultraviolet rays, X-rays or an electron beam. A current flowing between the pair of electrodes is measured during the voltage application time. The energy rays irradiation causes a surface leakage current, which is caused by adhered substances, to start to flow, and when the adhered substances have been eliminated perfectly, a relatively large current caused by the adhered substances disappears. Perfect elimination of the adhered substances can be verified by confirming that the relatively large current has disappeared.Type: ApplicationFiled: August 29, 2001Publication date: March 14, 2002Applicant: Rigaku CorporationInventors: Ryo Hattori, Yoshitugu Yamamoto, Yoshihiro Notani, Shinichi Miyakuni, Taisei Hirayama, Koichiro Ito
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Patent number: 6355951Abstract: In a field effect transistor such as high output FET or low noise HEMT, a layer for facilitating re-combination of carriers (for example a superlattice buffer layer), an undoped compound semiconductor layer having a higher resistance than a channel layer and the channel layer made of a compound semiconductor are layered successively. In the layer for facilitating re-combination of carriers, for example, oxygen of high concentration is introduced, to facilitate the non-radiative recombination which shortens the life of injected carriers. The layer for facilitating re-combination of carriers is also formed by forming the superlattice layer at a lower temperature than the channel layer. Thus, efficiency and voltageproofness on high frequency, high output power operation is improved further, and noises can be decreased further on high frequency, low noise operation.Type: GrantFiled: December 16, 1999Date of Patent: March 12, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Ryo Hattori
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Patent number: 6043520Abstract: A hetero-junction bipolar transistor having high reliability wherein a ballast resistance is exactly controlled and deterioration in current stability is eliminated. A GaAs ballast resistor layer is provided in a hetero-junction bipolar transistor having a GaAs emitter layer, an InGaP spacer layer, and a GaAs base layer, preventing a notch from being formed in the conduction band at the interface of the emitter layer and the ballast resistor layer, exactly controlling the ballast resistance. The AlGaAs layer is prevented from trapping impurities and the current stability is prevented from deteriorating.Type: GrantFiled: September 18, 1998Date of Patent: March 28, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshitsugu Yamamoto, Ryo Hattori
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Patent number: 5864169Abstract: A semiconductor device includes a semiconductor substrate having opposite front and rear surfaces; a semiconductor element disposed on the front surface of the semiconductor substrate and including an electrode; a PHS for dissipating heat generated in the semiconductor element, the PHS including a metal layer and disposed on the rear surface of the semiconductor substrate; a via-hole including a through-hole penetrating through the semiconductor substrate from the front surface to the rear surface and having an inner surface, and a metal disposed in the through-hole and contacting the PHS; and an air-bridge wiring including a metal film and having first and second portions, the air-bridge contacting the electrode of the semiconductor element at the first portion and contacting the metal of the via-hole at the second portion.Type: GrantFiled: July 19, 1995Date of Patent: January 26, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Teruyuki Shimura, Masayuki Sakai, Ryo Hattori, Hiroshi Matsuoka, Manabu Katoh
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Patent number: 5777389Abstract: A method for fabricating a semiconductor device includes: successively laminating a pair or more pairs of Ti and Al thin films on an n type GaAs substrate thereby to form Ti/Al laminated films; and performing thermal processing to the n type GaAs substrate and the Ti/Al laminated films at a temperature lower than the temperature at which Al of the Ti/Al laminated films and GaAs of the n type GaAs layer react with each other, to make the Ti/Al laminated films have ohmic junction with the n type GaAs layer thereby to form an ohmic electrode. Therefore, the Ti/Al laminated layer film comprising materials which are not likely to intrude into the n type GaAs layer is alloyed to Al.sub.3 Ti alloy by the annealing, and during the annealing, Ga atoms are out-migrated from the n type GaAs layer, and the Si atoms as dopants in the n type GaAs layer are present in the junction interface of the n type GaAs layer with the Ti/Al laminated layer film, thereby to form an ohmic contact.Type: GrantFiled: February 1, 1996Date of Patent: July 7, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Ryo Hattori
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Patent number: 5726468Abstract: A semiconductor device includes a semiconductor substrate; a first active layer disposed on the semiconductor substrate; a second active layer disposed on the first active layer; a first electrode including a lower stage disposed on the second active layer and an upper stage disposed on the lower stage and having an overhanging portion protruding from the lower stage; an insulating film continuously covering a surface of the second active layer, a side surface of the lower stage of the first electrode, and a lower surface and a side surface of the overhanging portion of the upper stage; and a second electrode disposed on the surface of the first active layer at opposite sides of the second active layer, self-aligned with the second active layer. The distance between the second electrode and the second active layer is minimized and the thickness of the second electrode can be about 7000 .ANG., minimizing the resistance of the first active layer and improving high frequency characteristics.Type: GrantFiled: March 13, 1996Date of Patent: March 10, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomoki Oku, Hirofumi Nakano, Shinichi Miyakuni, Teruyuki Shimura, Ryo Hattori
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Patent number: 5693560Abstract: An electrode of a semiconductor device includes an oxygen absorbing layer disposed on a surface of a semiconductor layer and a refractory metal layer disposed on the oxygen absorbing layer. Oxygen of a spontaneous oxide film on the semiconductor layer is taken to the oxygen absorbing layer, preventing the formation of interface levels within an interface metamorphic layer, preventing I.sub.d drifting.Type: GrantFiled: September 22, 1995Date of Patent: December 2, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Ryo Hattori, Yasutaka Kohno, deceased, Tetsuro Kunii
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Patent number: 5587792Abstract: An interference waveform dispersion spectrum of light reflected from a multi-layer film is compared to a waveform obtained by numerical calculation using an optical characteristic matrix. Respective layer thickness values obtained from the calculated analysis of the Spatial interference waveform are subjected to waveform fitting with actually measured values. The theoretical interference spectrum is recalculated while changing approximate values of the layer thicknesses until a match is obtained to obtain precise respective layer thicknesses. The thicknesses of respective layers of a thin multi-layer film of submicron thicknesses can be non-destructively measured exactly and stably without direct contact.Type: GrantFiled: October 11, 1995Date of Patent: December 24, 1996Inventors: Seiji Nishizawa, Tokuji Takahashi, Ryo Hattori
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Patent number: 5523840Abstract: An interference waveform dispersion spectrum of light reflected from a multi-layer film is compared to a waveform obtained by numerical calculation using an optical characteristic matrix. Respective layer thickness values obtained from the calculated analysis of the Spatial interference waveform are subjected to waveform fitting with actually measured values. The theoretical interference spectrum is recalculated while changing approximate values of the layer thicknesses until a match is obtained to obtain precise respective layer thicknesses. The thicknesses of respective layers of a thin multi-layer film of submicron thicknesses can be non-destructively measured exactly and stably without direct contact.Type: GrantFiled: June 21, 1994Date of Patent: June 4, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Seiji Nishizawa, Tokuji Takahashi, Ryo Hattori
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Patent number: 5498572Abstract: A method for manufacturing a semiconductor device including forming an electrode on a part of a semiconductor substrate, depositing an insulating film on the semiconductor substrate and on the electrode, and forming a contact hole penetrating through the insulating film to expose a part of the electrode; forming a barrier metal layer on the electrode in the contact hole, on the internal side surface of the contact hole, and on the surface of the insulating film; and depositing a metal layer on the barrier metal layer and patterning the metal layer and the barrier metal layer to form a wiring layer wherein the barrier metal layer comprises a metal that does not form an intermetallic material by solid state diffusion with either of the electrode and the metal layer even at elevated temperatures.Type: GrantFiled: September 30, 1994Date of Patent: March 12, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshihiko Shiga, Ryo Hattori, Tomoki Oku
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Patent number: 5496748Abstract: A method for producing a refractory metal gate electrode includes forming a patterning mask layer that is dissolved in a solution including hydrogen ions and having an aperture on a semiconductor substrate; forming a gate metal layer having an ionization potential larger than hydrogen on the entire surface of the patterning mask layer; forming a low resistance metal layer of a predetermined configuration having an ionization potential smaller than hydrogen on the gate metal layer; covering at least an upper surface of the low resistance metal layer with a film that has no reductive reaction with a solution including hydrogen ions; and removing the patterning mask layer using a solution including hydrogen ions after patterning the gate metal layer.Type: GrantFiled: September 13, 1994Date of Patent: March 5, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Ryo Hattori, Yasutaka Kohno
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Patent number: 5371596Abstract: An apparatus for measuring the thickness of a semiconductor layer includes a light source emitting light; an interferometer producing modulated interference light by modulating the light from the light source; an optical system including a light transmission member for introducing the modulated interference light into a measurement sample including at least one film on a substrate; a light detecting element for detecting the modulated interference light reflected from the film and producing an output signal in response; an extracting element for extracting a film interference component having a waveform from the output signal; and an element for calculating the thickness of the film from the waveform of the output signal component. The light detecting element includes a plurality of photodetectors having respective photometric wavenumber ranges that overlap.Type: GrantFiled: March 8, 1993Date of Patent: December 6, 1994Assignees: JASCO Corporation, Mitsubishi Denki Kabushiki KaishaInventors: Ryo Hattori, Seizi Nishizawa, Tokuji Takahashi, Ryoichi Fukasawa
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Patent number: 5227861Abstract: An apparatus for and a method of evaluating a multilayer thin film of the present invention. An interference light beam in a predetermined wave number region is projected as a parallel beam onto a multilayer thin film sample and the interference light beam reflected by the sample is detected to find an interferogram. The interferogram is subject to Fourier transform, filtering and reverse Fourier transform so that a spatialgram is provided. Thereby the variation in incident angle of the light beam incident on the sample and in incident surface is reduced, and the spatialgram can be provided with accurate information of the multilayer thin film.Type: GrantFiled: September 24, 1990Date of Patent: July 13, 1993Assignees: Mitsubishi Denki Kabushiki Kaisha, Jasco CorporationInventors: Seizi Nishizawa, Ryoichi Fukazawa, Tokuzi Takahashi, Ryo Hattori
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Patent number: 5179040Abstract: A novel semiconductor laser device includes a P-type semiconductor substrate, an N-type InP current blocking layer on the substrate, a P-type InP buried layer of which has the same thickness as and is surrounded by the first current blocking layer, and a ridge, on the buried layer, having a double heterojunction structure therein and including a stack of a planar P-type first InP cladding layer, a planar InGaAsP active layer, and a planar N-type second InP cladding layer. The ridge has a width of the same order as that of the buried layer. A P-type InP current blocking layer is disposed on the N-type current blocking layer burying the ridge and an N-type contact layer is formed opposite and in contact with the P-type current blocking layer and the N-type cladding layer. The conductivity types of the layers can be reversed.Type: GrantFiled: September 23, 1991Date of Patent: January 12, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Ryo Hattori
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Patent number: 5111471Abstract: A novel semiconductor laser device includes a P-type semiconductor substrate, an N-type InP current blocking layer on the substrate, a P-type InP buried layer of which has the same thickness as and is surrounded by the first current blocking layer, and a ridge, on the buried layer, having a double heterojunction structure therein and including a stack of a planar P-type first InP cladding layer, a planar InGaAsP active layer, and a planar N-type second InP cladding layer. The ridge has a width of the same order as that of the buried layer. A P-type InP current blocking layer is disposed on the N-type current blocking layer burying the ridge and an N-type contact layer is formed opposite and in contact with the P-type current blocking layer and the N-type cladding layer. The conductivity types of the layers can be reversed.Type: GrantFiled: January 7, 1991Date of Patent: May 5, 1992Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Ryo Hattori