Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

Abstract: A data transfer control device is provided having a plurality of shift registers connected through said multiplexers in a closed loop, a selector connected to the inputs of said multiplexer and for selecting a transfer destination of display data according to a common electrode select signal of a display unit, and a gate for selecting the polarity of the display data to be loaded into said shift registers according to the polarity of common output signals for scanning common electrodes of said display unit.

Abstract: A liquid crystal driver circuit has first to fourth resistors serially connected between a positive power source terminal and a reference power source terminal, first and second MOS transistors respectively connected in parallel with the first and fourth resistors, a common electrode driver circuit for generating common electrode bias signals in accordance with common electrode selection signals, and a segment electrode driver circuit for generating segment electrode bias signals in accordance with segment data. A third switching MOS transistor is coupled between the reference power source terminal and the series circuit of the first to fourth resistors.

Abstract: A power source voltage change discrimination circuit includes a voltage selection circuit for selectively supplying the greater one of main and auxiliary power source voltages, and a series circuit of a resistor and a capacitor coupled between the output terminal of the voltage selection circuit and ground. There is further provided a Schmitt circuit having hysteresis characteristics whose input terminal is coupled to a junction of the resistor and capacitor.