Abstract: A result confirmation unit (204) computes a state space probability that is a probability that a verification target device (300) has not correctly prepared a state space having a quantum state stored therein, a Pauli measurement probability that is a probability that the verification target device (300) has not correctly performed Pauli Z measurement and Pauli X measurement, and a magic state probability that is a probability that the verification target device (300) has not generated a magic state of CCZ. Then, using the state space probability, the Pauli measurement probability, and the magic state probability, the result confirmation unit (204) computes a degree of approximation between a quantum state and the magic state of CCZ at the verification target device (300) and measurement accuracies of the Pauli Z measurement and the Pauli X measurement on the quantum state at the verification target device (300).

Abstract: An information processing apparatus includes a processor configured to accept feature information on a specification of a target circuit to be designed. The processor is configured to refer to first correspondence information in which a plurality of parameter values are associated with respective index values for each piece of feature information on specifications of respective circuits to be configured in an integrated circuit. The processor is configured to calculate, for each of a plurality of combinations of parameter values related to the accepted feature information, a sum of the index values associated with respective parameter values included in the relevant combination of parameter values. The processor is configured to select one or more combinations of parameter values from among the plurality of combinations of parameter values on basis of the calculated sums. The processor is configured to output the selected combinations of parameter values.

Abstract: An information processing apparatus includes a memory and a processor: where the memory stores first correspondence information in which, regarding each of regions delimited based on a level of possibility that a path included in a circuit does not meet timing constraints, region information representing the region and a range of a value of an item relating to delay of the path are associated with each other and second correspondence information in which, regarding a certain region, region information that represents the certain region and countermeasure information that represents a countermeasure against delay of the path whose value of the item corresponds to the certain region are associated with each other; and the processor outputs the countermeasure information by referring to the first and the second correspondence information, regarding a value of the item relating to delay of a path included in a target circuit of verification.

Abstract: An information processing apparatus for design assistance including: a memory storing first correspondence relationship information in which feature information of a circuit and a value to be set to a parameter for use to cause an integrated circuit capable of configuring the circuit therein to configure the circuit are associated with each other, and second correspondence relationship information in which each of multiple values settable to the parameter and an improvement level of a performance of the circuit configured by the integrated circuit with the value set to the parameter are associated with each other; and a processor receives feature information related of a target circuit to be designed; if a value of a parameter set to the integrated circuit to configure the target circuit satisfies a predetermined constraint, the received feature information and the value are stored and accumulated in the first correspondence relationship information.

Abstract: In an LNG tank, a dike is formed by arranging precast blocks in the circumferential direction and layering the precast blocks in the vertical direction. Each of the precast blocks has loop joints on the top, bottom, left, and right side faces, and concrete is deposited between each two precast blocks adjacent in the circumferential direction and the vertical direction, whereby masonry joints are formed in the vertical direction and the circumferential direction. Prestress is imparted to the dike by PC steel members. The PC steel members are provided in the circumferential direction and the vertical direction of the dike, and are arranged so as to avoid the masonry joints in the circumferential direction and the vertical direction. Therefore, it is possible to construct the dike in a short time, and it is possible to provide a tank or the like that can reduce the construction period.

Abstract: In an LNG tank, a dike is formed by arranging precast blocks in the circumferential direction and layering the precast blocks in the vertical direction. Each of the precast blocks has loop joints on the top, bottom, left, and right side faces, and concrete is deposited between each two precast blocks adjacent in the circumferential direction and the vertical direction, whereby masonry joints are formed in the vertical direction and the circumferential direction. Prestress is imparted to the dike by PC steel members. The PC steel members are provided in the circumferential direction and the vertical direction of the dike, and are arranged so as to avoid the masonry joints in the circumferential direction and the vertical direction. Therefore, it is possible to construct the dike in a short time, and it is possible to provide a tank or the like that can reduce the construction period.

Abstract: An information processing apparatus includes a processor configured to accept feature information on a specification of a target circuit to be designed. The processor is configured to refer to first correspondence information in which a plurality of parameter values are associated with respective index values for each piece of feature information on specifications of respective circuits to be configured in an integrated circuit. The processor is configured to calculate, for each of a plurality of combinations of parameter values related to the accepted feature information, a sum of the index values associated with respective parameter values included in the relevant combination of parameter values. The processor is configured to select one or more combinations of parameter values from among the plurality of combinations of parameter values on basis of the calculated sums. The processor is configured to output the selected combinations of parameter values.

Abstract: An information processing apparatus includes a memory and a processor: where the memory stores first correspondence information in which, regarding each of regions delimited based on a level of possibility that a path included in a circuit does not meet timing constraints, region information representing the region and a range of a value of an item relating to delay of the path are associated with each other and second correspondence information in which, regarding a certain region, region information that represents the certain region and countermeasure information that represents a countermeasure against delay of the path whose value of the item corresponds to the certain region are associated with each other; and the processor outputs the countermeasure information by referring to the first and the second correspondence information, regarding a value of the item relating to delay of a path included in a target circuit of verification.

Abstract: An information processing apparatus for design assistance including: a memory storing first correspondence relationship information in which feature information of a circuit and a value to be set to a parameter for use to cause an integrated circuit capable of configuring the circuit therein to configure the circuit are associated with each other, and second correspondence relationship information in which each of multiple values settable to the parameter and an improvement level of a performance of the circuit configured by the integrated circuit with the value set to the parameter are associated with each other; and a processor receives feature information related of a target circuit to be designed; if a value of a parameter set to the integrated circuit to configure the target circuit satisfies a predetermined constraint, the received feature information and the value are stored and accumulated in the first correspondence relationship information.

Abstract: A receiving circuit that receives differential data strobe signals between a controller and a memory, the receiving circuit includes: a first receiver that compares one of the differential data strobe signals to the other, output a high logic value when the one of the differential data strobe signals is higher than the other, and output a low logic value when the one is lower than the other; a second receiver that compares one of the differential data strobe signals to a strobe reference voltage, output a high logic value when the one of the differential data strobe signals is higher than the strobe reference voltage, and output a low logic value when the one of the differential data strobe signals is lower than the strobe reference voltage; and a determination circuit that outputs a logical OR of an output of the first receiver and an output of the second receiver.

Abstract: An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second signal from the DQ signal based on a falling edge of the DQS signal. Variable delay adding units give the first signal a first delay based on a phase difference between an internal clock signal and the rising edge of the DQS signal and give the second signal a second delay based on a phase difference between the internal clock signal and the falling edge of the DQS signal. Data capturing units capture, based on the internal clock signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given.

Abstract: A receiving circuit that receives differential data strobe signals between a controller and a memory, the receiving circuit includes: a first receiver that compares one of the differential data strobe signals to the other, output a high logic value when the one of the differential data strobe signals is higher than the other, and output a low logic value when the one is lower than the other; a second receiver that compares one of the differential data strobe signals to a strobe reference voltage, output a high logic value when the one of the differential data strobe signals is higher than the strobe reference voltage, and output a low logic value when the one of the differential data strobe signals is lower than the strobe reference voltage; and a determination circuit that outputs a logical OR of an output of the first receiver and an output of the second receiver.

Abstract: An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second signal from the DQ signal based on a falling edge of the DQS signal. Variable delay adding units give the first signal a first delay based on a phase difference between an internal clock signal and the rising edge of the DQS signal and give the second signal a second delay based on a phase difference between the internal clock signal and the falling edge of the DQS signal. Data capturing units capture, based on the internal clock signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given.

Abstract: A hold error correction method for complicated large scale integration in a semiconductor is provided. Based on timing analyses, hold error path start point information including a set of a hold error amount at a start point and a minimum value in set-up margins for all data paths starting from the start point, and hold error path end point information including a set of a hold error amount at an end point and a minimum value in set-up margins for all data paths reaching the end point, in association with a failed hold error path, is obtained. The hold error path is classified based on whether the hold error is correctable according to the obtained information. The correctable hold error path is grouped based on a certain criterion. Finally, which of the start point and the end point a delay buffer is inserted into is determined per group.

Abstract: There is provided a circuit design apparatus that performs logic design for realizing a reduction of power consumption and circuit simplification. A circuit design apparatus interprets RTL of a design target to perform structure analysis thereof (S2), estimates generation of a clock gating based on a result of the structure analysis, detects RTL description of an EN generation logic (S3), and detects the same EN generation logic (S4). The apparatus determines an insertion location of the clock gating circuit and reorganization of logical hierarchies based on the detected EN generation logic (S5), instructs logical hierarchy reorganization to be performed in logic synthesis (S8) and performs design change processing (S6). The apparatus performs logic synthesis based on RTL after design change and instruction of logical hierarchy reorganization (S10), and layouts a concrete circuit configuration (S12).