Patents by Inventor Ryo Murata
Ryo Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260180471Abstract: A power converter includes first and second switching elements connected in series between first and second DC lines, third and fourth switching elements connected in series between the second DC line and a third DC line, an AC terminal, and a multilevel circuit. The multilevel circuit is connected between a first point of connection between the first and second switching elements and a second point of connection between the third and fourth switching elements, and the AC terminal. A filter includes a reactor having a first terminal connected to the AC terminal, and a capacitor connected between a second terminal of the reactor and the second DC line. The multilevel circuit mutually converts a first DC voltage received by the first point of connection and a third DC voltage received by the second point of connection, and a first AC voltage having at least five voltage values.Type: ApplicationFiled: October 18, 2023Publication date: June 25, 2026Applicant: TMEIC CorporationInventors: Ryo MURATA, Tomohiro TANAKA
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Publication number: 20250357781Abstract: This uninterruptible power supply device includes: a semiconductor switch that is connected between a bypass AC power supply and a load, is turned on when the bypass AC power supply is normal, and is turned off when the bypass AC power supply has a power failure; and an inverter that converts DC power supplied from an AC power supply or a battery into AC power and supplies the AC power to the load when the bypass AC power supply has a power failure, and supplies an assist current to the load if a load current is larger than a threshold current when the bypass AC power supply is normal, the assist current being a difference between the load current and the threshold current. Therefore, even if the load current is increased by load variation, the current flowing through the semiconductor switch can be maintained at the threshold current or lower.Type: ApplicationFiled: April 13, 2023Publication date: November 20, 2025Applicant: TMEIC CorporationInventors: Ryogo IMANISHI, Kazunori SANADA, Ryo MURATA
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Patent number: 11939881Abstract: A platform of a gas turbine rotor blade according to one embodiment includes a groove portion recessed from an end surface on a trailing edge side toward a leading edge side. A bottom portion of the groove portion overlaps at least a blade-shaped portion when viewed from a radial direction.Type: GrantFiled: March 23, 2023Date of Patent: March 26, 2024Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Ryo Murata, Yuji Komagome, Naoya Tatsumi, Hiroki Kitada, Shunsuke Torii
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Publication number: 20230392505Abstract: A platform of a gas turbine rotor blade according to one embodiment includes a groove portion recessed from an end surface on a trailing edge side toward a leading edge side. A bottom portion of the groove portion overlaps at least a blade-shaped portion when viewed from a radial direction.Type: ApplicationFiled: March 23, 2023Publication date: December 7, 2023Inventors: Ryo MURATA, Yuji KOMAGOME, Naoya TATSUMI, Hiroki KITADA, Shunsuke TORII
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Patent number: 10483113Abstract: There is provided a TFT substrate that prevents corrosion of a gate electrode and a method for manufacturing the TFT substrate. The TFT substrate comprises a substrate; a gate comprising a gate electrode and a gate wiring, the gate comprising copper and formed on one surface of the substrate; a protection film to cover the gate; an insulation film formed on the protection film; a semiconductor film formed on the insulation film; and a source and a drain formed on the semiconductor film and facing each other with a space therebetween above the gate electrode, wherein the protection film covers entire exposed surface of the gate.Type: GrantFiled: June 14, 2018Date of Patent: November 19, 2019Assignee: Sakai Display Products CorporationInventor: Ryo Murata
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Publication number: 20180294160Abstract: There is provided a TFT substrate that prevents corrosion of a gate electrode and a method for manufacturing the TFT substrate. The TFT substrate comprises a substrate; a gate comprising a gate electrode and a gate wiring, the gate comprising copper and formed on one surface of the substrate; a protection film to cover the gate; an insulation film formed on the protection film; a semiconductor film formed on the insulation film; and a source and a drain formed on the semiconductor film and facing each other with a space therebetween above the gate electrode, wherein the protection film covers entire exposed surface of the gate.Type: ApplicationFiled: June 14, 2018Publication date: October 11, 2018Inventor: Ryo MURATA
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Patent number: 10031361Abstract: A liquid crystal layer is disposed on a second glass substrate side between a first glass substrate and a second glass substrate, a first insulating film and a second insulating film are formed in this order on a surface of the first glass substrate that is disposed on the liquid crystal layer side, the outer edge portion of the liquid crystal layer is surrounded by a sealing material, and a slit is formed in a part or the whole of the peripheral edge portion of the second insulating film disposed on a further inner side than a position at which the second insulating film overlaps the sealing material. In addition, a slit formed in a peripheral edge portion of the first insulating film that corresponds to the sealing material is filled with a gate insulating film having a higher barrier property for gas and/or liquid than the first insulating film.Type: GrantFiled: May 23, 2014Date of Patent: July 24, 2018Assignee: Sakai Display Products CorporationInventors: Ryo Murata, Shinji Koiwa, Yoshiaki Matsushima, Satoru Utsugi
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Patent number: 9733505Abstract: A liquid crystal layer is disposed on a second glass substrate side between a first glass substrate and the second glass substrate, a first insulating film and a second insulating film are formed in this order on a surface of the first glass substrate on the liquid crystal layer side, the outer edge portion of the liquid crystal layer is surrounded by a sealing material, and a plurality of TFTs are insulated from each other by the first insulating film and the second insulating film. A gate insulating film included in the second insulating film is so formed as to have a higher barrier property for gas and/or liquid than the first insulating film, and a groove having a bottom formed with the same material as a part of the material for forming the TFT is formed at a part or the whole of a peripheral edge portion of the second insulating film which is located more inside than a position at which the second insulating film overlaps the sealing material.Type: GrantFiled: May 29, 2014Date of Patent: August 15, 2017Assignee: Sakai Display Products CorporationInventors: Nobutake Nodera, Ryo Murata, Kazuki Nakao, Takahiro Takatsu
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Publication number: 20160109747Abstract: A liquid crystal layer is disposed on a second glass substrate side between a first glass substrate and the second glass substrate, a first insulating film and a second insulating film are formed in this order on a surface of the first glass substrate on the liquid crystal layer side, the outer edge portion of the liquid crystal layer is surrounded by a sealing material, and a plurality of TFTs are insulated from each other by the first insulating film and the second insulating film. A gate insulating film included in the second insulating film is so formed as to have a higher barrier property for gas and/or liquid than the first insulating film, and a groove having a bottom formed with the same material as a part of the material for forming the TFT is formed at a part or the whole of a peripheral edge portion of the second insulating film which is located more inside than a position at which the second insulating film overlaps the sealing material.Type: ApplicationFiled: May 29, 2014Publication date: April 21, 2016Applicant: Sakai Display Products CorporationInventors: Nobutake Nodera, Ryo Murata, Kazuki Nakao, Takahiro Takatsu
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Publication number: 20160070133Abstract: A liquid crystal layer is disposed on a second glass substrate side between a first glass substrate and a second glass substrate, a first insulating film and a second insulating film are formed in this order on a surface of the first glass substrate that is disposed on the liquid crystal layer side, the outer edge portion of the liquid crystal layer is surrounded by a sealing material, and a slit is formed in a part or the whole of the peripheral edge portion of the second insulating film disposed on a further inner side than a position at which the second insulating film overlaps the sealing material. In addition, a slit formed in a peripheral edge portion of the first insulating film that corresponds to the sealing material is filled with a gate insulating film having a higher barrier property for gas and/or liquid than the first insulating film.Type: ApplicationFiled: May 23, 2014Publication date: March 10, 2016Inventors: Ryo Murata, Shinji Koiwa, Yoshiaki Matsushima, Satoru Utsugi
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Patent number: 8488043Abstract: An image apparatus records images of a subject corresponding to a photo opportunity without intensifying complex operations after the imaging. When a SLOW button is depressed, a process is started in which frame image data that is obtained at an imaging frame rate is stored sequentially in a buffer memory. The frame image data is read out from the buffer memory at a display frame rate that is set in advance, and images are displayed on a display device based on this frame image data. When a shutter key is depressed, the frame image data read out from the buffer memory is recorded to storage memory.Type: GrantFiled: September 28, 2007Date of Patent: July 16, 2013Assignee: Casio Computer Co., Ltd.Inventors: Ryo Murata, Takashi Onoda, Osamu Nojima
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Publication number: 20080079817Abstract: An image apparatus records images of a subject corresponding to a photo opportunity without intensifying complex operations after the imaging. When a SLOW button is depressed, a process is started in which frame image data that is obtained at an imaging frame rate is stored sequentially in a buffer memory. The frame image data is read out from the buffer memory at a display frame rate that is set in advance, and images are displayed on a display device based on this frame image data. When a shutter key is depressed, the frame image data read out from the buffer memory is recorded to storage memory.Type: ApplicationFiled: September 28, 2007Publication date: April 3, 2008Applicant: Casio Computer Co., Ltd.Inventors: Ryo Murata, Takashi Onoda, Osamu Nojima
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Patent number: D310032Type: GrantFiled: July 7, 1987Date of Patent: August 21, 1990Assignee: Casio Computer Co., Ltd.Inventor: Ryo Murata
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Patent number: D311141Type: GrantFiled: July 7, 1987Date of Patent: October 9, 1990Assignee: Casio Computer Co., Ltd.Inventor: Ryo Murata
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Patent number: D319800Type: GrantFiled: April 20, 1987Date of Patent: September 10, 1991Assignee: Casio Computer Co., Ltd.Inventor: Ryo Murata
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Patent number: D938321Type: GrantFiled: August 5, 2020Date of Patent: December 14, 2021Assignee: Toyota Jidosha Kabushiki KaishaInventors: Yukio Kushima, Ryo Murata
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Patent number: D1021711Type: GrantFiled: August 9, 2022Date of Patent: April 9, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Ryo Murata
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Patent number: D1043434Type: GrantFiled: August 9, 2022Date of Patent: September 24, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Mario Majdandzic, Manabu Hirokawa, Hideaki Iida, Ryo Murata
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Patent number: D1065620Type: GrantFiled: August 9, 2022Date of Patent: March 4, 2025Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Manabu Hirokawa, Ryo Murata
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Patent number: D1107592Type: GrantFiled: April 10, 2024Date of Patent: December 30, 2025Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Stephan Jubt Rasmussen, Ryo Murata, Hideaki Iida