Patents by Inventor Ryo Nemoto
Ryo Nemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951662Abstract: A foamed sheet including: a polylactic acid; and a filler, wherein the foamed sheet has a compressive stress of 0.2 Mpa or less when the cushioning coefficient of the foamed sheet is 10 or less; and wherein the foamed sheet has a puncture strength of 2 N or more when the sheet thickness of the foamed sheet is 2 mm.Type: GrantFiled: November 23, 2021Date of Patent: April 9, 2024Assignee: RICOH COMPANY, LTD.Inventors: Taichi Nemoto, Shizuka Hashida, Yoshimitsu Kumai, Ryo Miyakoshi, Tomoharu Miki
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Patent number: 7944338Abstract: In an RFID system including RFID tags each incorporating a sensor, accuracy of measurement by the sensor can be improved. For example, when measurements are performed several times by using RFID tags each incorporating a sensor unit, generation of a carrier directed from an RFID reader/writer to the RFID tags is stopped for a predetermined period every time when a measurement ends. By this means, the chip temperature of the RFID tag increased due to power consumption in each measurement can be reduced to, for example, ambient temperature every time when a measurement ends. Therefore, an error in measurement by the sensor unit can be reduced, thereby achieving accurate measurement.Type: GrantFiled: July 25, 2006Date of Patent: May 17, 2011Assignee: Hitachi, Ltd.Inventors: Ryo Nemoto, Hiroshi Yoshigi, Yoshiaki Yazawa, Kazuki Watanabe
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Patent number: 7764090Abstract: A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means.Type: GrantFiled: April 18, 2008Date of Patent: July 27, 2010Assignee: Hitachi, Ltd.Inventors: Hiroki Yamashita, Ryo Nemoto
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Patent number: 7649381Abstract: A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.Type: GrantFiled: December 14, 2007Date of Patent: January 19, 2010Assignee: Hitachi, Ltd.Inventors: Hiroki Yamashita, Fumio Yuuki, Ryo Nemoto, Hisaaki Kanai, Keiichi Yamamoto
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Publication number: 20090033431Abstract: The present invention provides a highly accurate oscillation circuit. For example, the oscillation circuit includes plural ring oscillator units RO1 and RO2 including inverter circuits IV of an odd number of stages, and an adding unit ADD that adds signals of output nodes RO—01 and RO—02 of the RO1 and RO2. It outputs an addition result of the ADD from an output node OSC_O as a clock signal, and feeds the output node OSC_O back to input nodes RO_I1 and RO_I2 of the RO1 and RO2. Thereby, for example, when each of delay times of the RO1 and RO2 disperses based on a normal distribution of standard deviation ?, the dispersion of a clock signal obtained from the OSC_O can be confined to ?/?{square root over (2)}.Type: ApplicationFiled: July 30, 2008Publication date: February 5, 2009Inventors: Hiroki Yamashita, Koji Fukuda, Ryo Nemoto, Hisaaki Kanai, Keiichi Yamamoto
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Publication number: 20080265973Abstract: A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means.Type: ApplicationFiled: April 18, 2008Publication date: October 30, 2008Inventors: Hiroki Yamashita, Ryo Nemoto
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Publication number: 20080157816Abstract: A level conversion circuit capable of realizing low-power/high-speed operation and suppression of variations in input/output characteristics due to variations in source voltage and temperature and device variation. The level conversion circuit comprises: a source follower circuit including a first transistor to input an AC signal of CML level thereto and a second transistor to input a control voltage thereto; and a control-voltage generating circuit to generate the control voltage to be inputted to the second transistor. The control-voltage generating circuit comprises: a replica source follower circuit which is a replica of the source follower circuit including a third transistor to input a central voltage of CML level thereto and a fourth transistor to input the control voltage thereto; and a comparator which controls the control voltage, thereby equalizing an output voltage of the replica source follower and a threshold voltage of a CMOS circuit.Type: ApplicationFiled: December 14, 2007Publication date: July 3, 2008Inventors: Hiroki Yamashita, Fumio Yuuki, Ryo Nemoto, Hisaaki Kanai, Keiichi Yamamoto
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Patent number: 7276891Abstract: To augment the temperature dependence of the voltage used to detect temperature in a semiconductor integrated circuit device having a temperature detection function, the operating power supply voltage of the semiconductor integrated circuit device needed to be enhanced. It becomes possible for such a semiconductor integrated circuit device to generate a voltage of great temperature dependence, even under a low operating power supply voltage, by including: a temperature-to-current converter which outputs a first electric current proportional to temperature; a current generator which outputs a second electric current having extremely small temperature dependence; a current subtracter which outputs a third electric current proportional to a differential current obtained by subtracting the second electric current from the first electric current; and a current-to-voltage converter which converts the third electric current into a voltage.Type: GrantFiled: October 25, 2005Date of Patent: October 2, 2007Assignee: Hitachi, Ltd.Inventors: Kazuki Watanabe, Ryo Nemoto, Yoshiaki Yazawa
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Publication number: 20070176772Abstract: In an RFID system including RFID tags each incorporating a sensor, accuracy of measurement by the sensor can be improved. For example, when measurements are performed several times by using RFID tags each incorporating a sensor unit, generation of a carrier directed from an RFID reader/writer to the RFID tags is stopped for a predetermined period every time when a measurement ends. By this means, the chip temperature of the RFID tag increased due to power consumption in each measurement can be reduced to, for example, ambient temperature every time when a measurement ends. Therefore, an error in measurement by the sensor unit can be reduced, thereby achieving accurate measurement.Type: ApplicationFiled: July 25, 2006Publication date: August 2, 2007Inventors: Ryo Nemoto, Hiroshi Yoshigi, Yoshiaki Yazawa, Kazuki Watanabe
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Patent number: 7250863Abstract: A measuring system enabled to simultaneously start measurement by a plurality of transponders by communication between a reader/writer and a plurality of transponders each with a built-in sensor is to be provided. In addition to an identifier SID intrinsic to a sensor and a chip identifier TID intrinsic to a transponder chip, a unique identifier UID combining the sensor SID and the chip TID is provided in each transponder. A reader/writer, in designating a transponder and transmitting a measurement command to it, invalidates the chip TID out of the UID of each transponder, validates only information regarding a sensor function, and transmits measurement commands including action commands unique to each type of sensor.Type: GrantFiled: January 18, 2005Date of Patent: July 31, 2007Assignee: Hitachi, Ltd.Inventors: Ryo Nemoto, Tadashi Oonishi, Kazuki Watanabe, Yoshiaki Yazawa, Yasushi Goto, Hiroshi Yoshigi
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Publication number: 20060103449Abstract: To augment the temperature dependence of the voltage used to detect temperature in a semiconductor integrated circuit device having a temperature detection function, the operating power supply voltage of the semiconductor integrated circuit device has needed to be enhanced. It becomes possible for such a semiconductor integrated circuit device to generate a voltage of great temperature dependence, even under a low operating power supply voltage, by including: a temperature-to-current converter which outputs a first electric current proportional to temperature; a current generator which outputs a second electric current having extremely small temperature dependence; a current subtracter which outputs a third electric current proportional to a differential current obtained by subtracting the second electric current from the first electric current; and a current-to-voltage converter which converts the third electric current into a voltage.Type: ApplicationFiled: October 25, 2005Publication date: May 18, 2006Inventors: Kazuki Watanabe, Ryo Nemoto, Toshiaki Yazawa
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Publication number: 20060066451Abstract: A measuring system enabled to simultaneously start measurement by a plurality of transponders by communication between a reader/writer and a plurality of transponders each with a built-in sensor is to be provided. In addition to an identifier SID intrinsic to a sensor and a chip identifier TID intrinsic to a transponder chip, a unique identifier UID combining the sensor SID and the chip TID is provided in each transponder. A reader/writer, in designating a transponder and transmitting a measurement command to it, invalidates the chip TID out of the UID of each transponder, validates only information regarding a sensor function, and transmits measurement commands including action commands unique to each type of sensor.Type: ApplicationFiled: January 18, 2005Publication date: March 30, 2006Inventors: Ryo Nemoto, Tadashi Oonishi, Kazuki Watanabe, Yoshiaki Yazawa, Yasushi Goto, Hiroshi Yoshigi