Abstract: According to one embodiment, a semiconductor memory device includes a first active area in a semiconductor substrate, memory cells on the semiconductor substrate, first bit lines, first line, a second line, a third line, and a fourth line. The first line extends in a direction that intersects with the first bit lines and transmits a control potential applied to unselected ones of second bit lines connected to the memory cells. The second line is electrically connected to the first line and extends along the first bit lines. The third line is electrically connected to the second line and extends in a direction that intersects with the first bit lines. The fourth line electrically connects both the third line and portions in the active area corresponding to nodes to which the control potential is applied.

Abstract: According to one embodiment, a semiconductor memory device includes a first active area in a semiconductor substrate, memory cells on the semiconductor substrate, first bit lines, first line, a second line, a third line, and a fourth line. The first line extends in a direction that intersects with the first bit lines and transmits a control potential applied to unselected ones of second bit lines connected to the memory cells. The second line is electrically connected to the first line and extends along the first bit lines. The third line is electrically connected to the second line and extends in a direction that intersects with the first bit lines. The fourth line electrically connects both the third line and portions in the active area corresponding to nodes to which the control potential is applied.

Abstract: A data processor having a debugging aid function capable of monitoring a plurality of kinds of internal buses from the outside and identifying each of the buses monitored is provided. A central processing unit (CPU), a debugging aid module, and other circuit modules are mounted on a semiconductor chip. The debugging aid module selects an information transmitting path in accordance with a trace condition from a plurality of information transmitting paths used for the operation of a central processing unit (CPU) or the like, holds trace information obtained according to the trace condition from the selected information transmitting path together with attribute information of the trace information in a buffer circuit, and outputs the information serially to the outside of the semiconductor chip. A plurality of kinds of internal buses can be monitored on the outside, and each of the buses monitored can be identified.

Abstract: Cultured cells flat-cultured on a permeable sheet is stacked on other flat-cultured cells together with the permeable sheet to construct a three-dimensional tissue. The three-dimensional tissue is transplanted into a living body. Alternatively, the three-dimensional tissue is stacked up in an artificial organ device to construct a stacked-up, three-dimensional bioartificial organ module. Colony form of the cultured cell can be controlled by using a microporous sheet as the permeable sheet and controlling positions of pores in the microporous sheet to design the form of the artificial organ.

Abstract: A data processor having a debugging aid function capable of monitoring a plurality of kinds of internal buses from the outside and identifying each of the buses monitored is provided. A central processing unit (CPU), a debugging aid module, and other circuit modules are mounted on a semiconductor chip. The debugging aid module selects an information transmitting path in accordance with a trace condition from a plurality of information transmitting paths used for the operation of a central processing unit (CPU) or the like, holds trace information obtained according to the trace condition from the selected information transmitting path together with attribute information of the trace information in a buffer circuit, and outputs the information serially to the outside of the semiconductor chip. A plurality of kinds of internal buses can be monitored on the outside, and each of the buses monitored can be identified.

Abstract: A data processor having a debugging aid function capable of monitoring a plurality of kinds of internal buses from the outside and identifying each of the buses monitored is provided. A central processing unit (CPU), a debugging aid module, and other circuit modules are mounted on a semiconductor chip. The debugging aid module selects an information transmitting path in accordance with a trace condition from a plurality of information transmitting paths used for the operation of a central processing unit (CPU) or the like, holds trace information obtained according to the trace condition from the selected information transmitting path together with attribute information of the trace information in a buffer circuit, and outputs the information serially to the outside of the semiconductor chip. A plurality of kinds of internal buses can be monitored on the outside, and each of the buses monitored can be identified.

Abstract: A data processor having a debugging aid function capable of monitoring a plurality of kinds of internal buses from the outside and identifying each of the buses monitored is provided. A central processing unit (CPU), a debugging aid module, and other circuit modules are mounted on a semiconductor chip. The debugging aid module selects an information transmitting path in accordance with a trace condition from a plurality of information transmitting paths used for the operation of a central processing unit (CPU) or the like, holds trace information obtained according to the trace condition from the selected information transmitting path together with attribute information of the trace information in a buffer circuit, and outputs the information serially to the outside of the semiconductor chip. A plurality of kinds of internal buses can be monitored on the outside, and each of the buses monitored can be identified.

Abstract: A differential amplifier comprises an n-channel MOS transistor to the gate of which an input voltage VIN1 is fed, and an n-channel MOS transistor to the gate of which an input voltage VIN2 is fed. A p-channel MOS transistor arranged in such a manner that, to the source thereof, a power source voltage Vcc is fed, and the gate and drain thereof are connected to the drain of the MOS transistor, and a p-channel MOS transistor arranged in such a manner that the gate thereof is connected to the drain of the MOS transistor, the drain thereof is connected to the drain of the MOS transistor, and the voltage at this drain is outputted as an output voltage VOUT, and the output current I of a constant-current source is set so that the transistors constituting a differential amplifier may operate in a weak inversion zone.