Patents by Inventor Ryo Takatsuki

Ryo Takatsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8076179
    Abstract: A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: December 13, 2011
    Assignee: Ryo Takatsuki
    Inventor: Ryo Takatsuki
  • Publication number: 20110230011
    Abstract: A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.
    Type: Application
    Filed: June 2, 2011
    Publication date: September 22, 2011
    Inventor: RYO TAKATSUKI
  • Patent number: 7977801
    Abstract: A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: July 12, 2011
    Inventor: Ryo Takatsuki
  • Publication number: 20090127716
    Abstract: A multi-chip module and an integrated structure of the present invention including: at least one of either a terminal unit formation area expanded type integrated circuit chip, or a terminal unit formation area identical type integrated circuit chip; terminal unit formation areas of these integrated circuits that are covered with protective layers, and expanded wiring units and terminal units formed in the protective layers; one or a plurality of the terminal unit formation area expanded type and the terminal unit formation area identical type integrated circuit chip components that are two-dimensionally or three-dimensionally aligned in further protective layers; a horizontal or a vertical wiring formed for arbitrarily connecting the plurality of the integrated circuit chip components in the further protective layers.
    Type: Application
    Filed: July 14, 2006
    Publication date: May 21, 2009
    Inventor: Ryo Takatsuki
  • Patent number: 5545922
    Abstract: A method is disclosed for constructing a dual-sided chip package onto a leadframe having a die pad and a set of lead fingers corresponding to the die pad. Integrated circuit dies are disposed onto each side of the die pad while the leadframe is supported with support blocks having cavities that accept the integrated circuit dies and that support each lead finger and that provide clearance for stitch bonds of the previously formed wire bonds. Thereafter, a one step plastic mold is formed around each assembly comprising the dual integrated circuit dies, the die pads, and the wire bonds.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: August 13, 1996
    Assignee: Intel Corporation
    Inventors: Suresh V. Golwalkar, Richard Foehringer, Michael Wentling, Ryo Takatsuki, Shigeo Kawashima, Keiichi Tsujimoto, Nobuaki Sato
  • Patent number: 5527740
    Abstract: A method is disclosed for constructing a dual-sided chip package onto a leadframe having a die pad and a set of lead fingers corresponding to the die pad. Integrated circuit dies are disposed onto each side of the die pad while the leadframe is supported with support blocks having cavities that accept the integrated circuit dies and that support each lead finger and that provide clearance for stitch bonds of the previously formed wire bonds. Thereafter, a one step plastic mold is formed around each assembly comprising the dual integrated circuit dies, the die pads, and the wire bonds.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: June 18, 1996
    Assignee: Intel Corporation
    Inventors: Suresh V. Golwalkar, Richard Foehringer, Michael Wentling, Ryo Takatsuki, Shigeo Kawashima, Keiichi Tsujimoto, Nobuaki Sato
  • Patent number: 5366933
    Abstract: A method for constructing a dual sided integrated circuit chip package. A leadframe is formed comprising a set of die pads, and a set of lead fingers corresponding to each die pad. An integrated circuit die is disposed onto a first side and a second side of each die pad. Each integrated circuit die is wire bonded to the corresponding lead fingers. The temperature during the second side die attach and wire bonding steps is controlled and/or compatible materials are selected to prevent warping of the leadframe, and special steps are also implemented to eliminate mold flash, plastic mold cracking and overcuring and increasing the adhesion.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: November 22, 1994
    Assignee: Intel Corporation
    Inventors: Suresh V. Golwalkar, Richard Foehringer, Michael Wentling, Ryo Takatsuki, Shigeo Kawashima