Abstract: A classification device (10) acquires an operation log related to operation information, identifies each operation performed by a user using the operation log, and creates a vector of each operation on the basis of a co-occurrence relationship between the identified operations. Then, the classification device (10) calculates a similarity between a predetermined number of operations adjacent to each other in chronological order using the created vector of each operation, determines a division point of the operations using the calculated similarity, and divides a time-series operation into operation sets on the basis of the division point. Then, the classification device (10) classifies the operation sets into classes on the basis of the number of types of operations common to the operation sets.

Abstract: In a method of checking an apparatus, failure time intervals of sections of an apparatus are divided into a plurality of failure time interval groups, each of which is indicated by a specific failure time interval. A plurality of check programs are classified into a plurality of groups corresponding to the plurality of failure time interval groups based on the failure time interval of the section corresponding to each of the plurality of check programs. A group execution time interval of each of the plurality of groups is determined based on the specific failure time interval. Then, each of the plurality of groups is executed based on the group execution time interval.

Abstract: An apparatus for testing a semiconductor IC, comprises electronic circuits in a number corresponding to the number of terminals of a memory to be tested. The electronic circuits each comprise a set of a waveform generator, a strobing pulse generator, and a logic comparator, the electronic circuit being a CMOS type LSI, wherein logic operation circuits in a semiconductor chip constituting a LSI and thermal control circuits are paired. The power consumption of the thermal control circuits is regulated by the output operation frequency of each of the logic operation circuits, the sum of the heating value of each of the logic operation circuits and the heating value of the thermal control circuits paired with the logic operation circuits are made constant, permitting timing accuracy to be stabilized independently of test frequency and test pattern.