Abstract: A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory with first storage areas. A controller executes a first read operation on a second storage area of the first storage areas. When an error correction in the first read operation fails, the controller acquires a first measured value being a value of a read voltage for suppressing the number of occurrences of error bits in the second storage area. The controller updates, on the basis of the first measured value, one of first candidate values of the read voltage with a second candidate value. When the error correction in a second read operation for a third storage area of the first storage areas fails, the controller executes the read operation once or more on the third storage area by using, as the read voltages, different first candidate values of the first candidate values.

Abstract: A memory system includes a nonvolatile memory including memory cells each configured to store first and second bits, and a memory controller. The memory controller is configured to: read first data by using a first voltage to a first read process that reads data corresponding to the first bit from the memory cells; read second data by using a second voltage to a second read process that reads data corresponding to the second bit from the memory cells; in a case where an error correction process of the first data is successful, determine a third voltage, based on the first data and third data that is obtained by error-correcting the first data; and update a first read voltage that is used to the first read process, from the first voltage to the third voltage.

Abstract: A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

Abstract: A memory system includes a non-volatile memory and a controller configured to divides an n-dimensional space into a plurality of regions by a plurality of hyperplanes, assign a representative point of a read level for reading data from a plurality of memory cells to each region, trace a branch node in the binary tree by determining whether a first read level is higher or lower than a voltage level at the branch node of the binary tree, determine a read level of a representative point assigned to a region correlated with a leaf node among the plurality of divided regions as a second read level corresponding to the first read level when reaching the leaf node of the binary tree by tracing the branch node in the binary tree, and cause the memory to read data of the cells by applying a voltage of the second read level.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells, and a memory controller. The memory controller is configured to: read first data from a first cell unit, using a first correction amount of a read voltage; identify an address of an error bit in the first data; update the first correction amount to a second correction amount, based on the first data and the address of the error bit of the first data; and read second data from a second cell unit different from the first cell unit, using a third correction amount based on the second correction amount.

Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a memory controller. The memory controller is configured to generate a histogram indicating, with respect to each of a plurality of threshold voltage levels for multi-level cell (MLC) reading, a number of memory cells at the threshold voltage level, based on data read from the plurality of memory cells using a plurality of reference read voltages, estimate a plurality of read voltages for MLC reading of the plurality of memory cells as estimation values by inputting the histogram into a read voltage estimation model, determine, through MLC reading of the plurality of memory cells using a plurality of sets of read voltages, a set of read voltages for MLC reading as observation values, and update one or more parameters of the read voltage estimation model based on the estimation values and the observation values.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells, and a memory controller. The memory controller is configured to: read first data from a first cell unit, using a first correction amount of a read voltage; identify an address of an error bit in the first data; update the first correction amount to a second correction amount, based on the first data and the address of the error bit of the first data; and read second data from a second cell unit different from the first cell unit, using a third correction amount based on the second correction amount.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a memory controller. The memory controller is configured to generate a histogram indicating, with respect to each of a plurality of threshold voltage levels for multi-level cell (MLC) reading, a number of memory cells at the threshold voltage level, based on data read from the plurality of memory cells using a plurality of reference read voltages, estimate a plurality of read voltages for MLC reading of the plurality of memory cells as estimation values by inputting the histogram into a read voltage estimation model, determine, through MLC reading of the plurality of memory cells using a plurality of sets of read voltages, a set of read voltages for MLC reading as observation values, and update one or more parameters of the read voltage estimation model based on the estimation values and the observation values.

Abstract: A memory system includes a non-volatile memory and a controller configured to divides an n-dimensional space into a plurality of regions by a plurality of hyperplanes, assign a representative point of a read level for reading data from a plurality of memory cells to each region, trace a branch node in the binary tree by determining whether a first read level is higher or lower than a voltage level at the branch node of the binary tree, determine a read level of a representative point assigned to a region correlated with a leaf node among the plurality of divided regions as a second read level corresponding to the first read level when reaching the leaf node of the binary tree by tracing the branch node in the binary tree, and cause the memory to read data of the cells by applying a voltage of the second read level.

Abstract: According to one embodiment, in a memory system, a memory controller is configured to execute a first operation of observing an optimum value of a read voltage and updating a set value based on the observation result of the optimum value, at a predetermined time point of a plurality of time points for updating the set value of the read voltage for a plurality of memory cells, and execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point.

Abstract: According to an embodiment, a memory system includes a plurality of memory cells and a memory controller. The memory controller executes a read operation on the plurality of memory cells using one or more reference read voltages to acquire a histogram representing the number of memory cells with respect to a threshold voltage. The memory controller inputs the histogram to a trained neural network model including an output layer for outputting one or more actual read voltages to read data from the memory cells. The memory controller executes a read operation on the memory cells using the one or more actual read voltages output from the output layer.

Abstract: According to one embodiment, in a memory system, a memory controller is configured to execute a first operation of observing an optimum value of a read voltage and updating a set value based on the observation result of the optimum value, at a predetermined time point of a plurality of time points for updating the set value of the read voltage for a plurality of memory cells, and execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point.

Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

Abstract: A memory controller performs a reference read on a plurality of memory cells using reference read voltages, generates a histogram indicating the number of memory cells in different threshold voltage bins based on results of the reference read, estimates actual read voltages based on the histogram and a first estimation function, and reads data using the actual read voltages. When reading of the data with the actual read voltages estimated using the first estimation function fails, the memory controller estimates actual read voltages using a second estimation function different from the first estimation function and reads the data with the actual read voltages estimated using the second estimation function.

Abstract: A memory controller performs a reference read on a plurality of memory cells using reference read voltages, generates a histogram indicating the number of memory cells in different threshold voltage bins based on results of the reference read, estimates actual read voltages based on the histogram and a first estimation function, and reads data using the actual read voltages. When reading of the data with the actual read voltages estimated using the first estimation function fails, the memory controller estimates actual read voltages using a second estimation function different from the first estimation function and reads the data with the actual read voltages estimated using the second estimation function.

Abstract: According to an embodiment, a memory system includes a plurality of memory cells and a memory controller. The memory controller executes a read operation on the plurality of memory cells using one or more reference read voltages to acquire a histogram representing the number of memory cells with respect to a threshold voltage. The memory controller inputs the histogram to a trained neural network model including an output layer for outputting one or more actual read voltages to read data from the memory cells. The memory controller executes a read operation on the memory cells using the one or more actual read voltages output from the output layer.