Patents by Inventor Ryohei Inazawa

Ryohei Inazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9117972
    Abstract: The light-emitting device has a semiconductor layer including a p-layer, a light-emitting layer, and an n-layer, which are formed of a Group III nitride semiconductor, and an n-electrode on the n-layer. The device also has a device isolation trench which runs along the outer periphery of the semiconductor layer and which provides the semiconductor layer with a mesa shape; and an insulation film continuously provided on first to third regions, the first region being an outer peripheral region of the n-layer, the second region being the side surface of the trench, and the third region being the bottom surface of the device isolation trench. The n-electrode consists of two pad portions and a wire trace portion. The outer peripheral wire trace portion is formed as a frame completely contouring the periphery of the device.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: August 25, 2015
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Koichi Mizutani, Ryohei Inazawa, Yuhei Ikemoto, Tomoyuki Tainaka
  • Patent number: 8324083
    Abstract: A method for producing a Group III nitride compound semiconductor element includes growing an epitaxial layer containing a Group III nitride compound semiconductor using a different kind of substrate as an epitaxial growth substrate, adhering a supporting substrate to the top surface of the epitaxial growth layer through a conductive layer, and then removing the epitaxial growth substrate by laser lift-off. Before adhesion of the epitaxial layer and the supporting substrate, a first groove that at least reaches an interface between the bottom surface of the epitaxial layer and the epitaxial growth substrate from the top surface of the epitaxial layer formed on the epitaxial growth substrate and acts as an air vent communicating with the outside of a wafer when the epitaxial layer and the supporting substrate are joined to each other.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: December 4, 2012
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Masanobu Ando, Tomoharu Shiraki, Masahiro Ohashi, Naoki Arazoe, Ryohei Inazawa
  • Patent number: 8003418
    Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor light-emitting device, wherein a contact electrode is formed on an N-polar surface of an n-type layer through annealing at 350° C. or lower. In the case where, in a Group III nitride-based compound semiconductor device produced by the laser lift-off process, a contact electrode is formed, through annealing at 350° C. or lower, on a micro embossment surface (i.e., a processed N-polar surface) of an n-type layer from vanadium, chromium, tungsten, nickel, platinum, niobium, or iron, when a pseudo-silicon-heavily-doped layer is formed on the micro embossment surface (i.e., N-polar surface) of the n-type layer through treatment with a plasma of a silicon-containing compound gas, and treatment with a fluoride-ion-containing chemical is not carried out, ohmic contact is obtained, and low resistance is attained.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: August 23, 2011
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Umemura, Ryohei Inazawa, Koichi Goshonoo, Tomoharu Shiraki
  • Publication number: 20100248407
    Abstract: Provided is a method for producing a Group III nitride-based compound semiconductor light-emitting device, wherein a contact electrode is formed on an N-polar surface of an n-type layer through annealing at 350° C. or lower. In the case where, in a Group III nitride-based compound semiconductor device produced by the laser lift-off process, a contact electrode is formed, through annealing at 350° C. or lower, on a micro embossment surface (i.e., a processed N-polar surface) of an n-type layer from vanadium, chromium, tungsten, nickel, platinum, niobium, or iron, when a pseudo-silicon-heavily-doped layer is formed on the micro embossment surface (i.e., N-polar surface) of the n-type layer through treatment with a plasma of a silicon-containing compound gas, and treatment with a fluoride-ion-containing chemical is not carried out, ohmic contact is obtained, and low resistance is attained.
    Type: Application
    Filed: March 30, 2010
    Publication date: September 30, 2010
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Toshiya Umemura, Ryohei Inazawa, Koichi Goshonoo, Tomoharu Shiraki
  • Patent number: 7781241
    Abstract: The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed on the top surface of the p-layer, and a first low-melting-point metal diffusion preventing layer, the low-melting-point metal diffusion preventing layer being formed on the top surface of the p-electrode; forming, from a dielectric material, a side-surface protective film so as to cover a side surface of each semiconductor device; bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and removing the base through the laser lift-off process.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: August 24, 2010
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Ryohei Inazawa, Toshiya Uemura
  • Publication number: 20100081256
    Abstract: A method for producing a Group III nitride compound semiconductor element includes growing an epitaxial layer containing a Group III nitride compound semiconductor using a different kind of substrate as an epitaxial growth substrate, adhering a supporting substrate to the top surface of the epitaxial growth layer through a conductive layer, and then removing the epitaxial growth substrate by laser lift-off. Before adhesion of the epitaxial layer and the supporting substrate, a first groove that at least reaches an interface between the bottom surface of the epitaxial layer and the epitaxial growth substrate from the top surface of the epitaxial layer formed on the epitaxial growth substrate and acts as an air vent communicating with the outside of a wafer when the epitaxial layer and the supporting substrate are joined to each other.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Toshiya Uemura, Masanobu Ando, Tomoharu Shiraki, Masahiro Ohashi, Naoki Arazoe, Ryohei Inazawa
  • Publication number: 20080149953
    Abstract: The method of the invention for producing a group III-V semiconductor device includes forming, on a base, a plurality of semiconductor devices isolated from one another, each semiconductor device having at least an n-layer proximal to the base, and a p-layer distal to the base, and having a p-electrode formed on the top surface of the p-layer, and a first low-melting-point metal diffusion preventing layer, the low-melting-point metal diffusion preventing layer being formed on the top surface of the p-electrode; forming, from a dielectric material, a side-surface protective film so as to cover a side surface of each semiconductor device; bonding the semiconductor device to a conductive support substrate via a low-melting-point metal layer; and removing the base through the laser lift-off process.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 26, 2008
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Masanobu Ando, Shigemi Horiuchi, Yoshinori Kinoshita, Ryohei Inazawa, Toshiya Uemura