Patents by Inventor Ryohei NEGA

Ryohei NEGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153892
    Abstract: According to one embodiment, an isolator includes first and second electrodes, first and second insulating portions, and a first dielectric portion. The first insulating portion is provided on the first electrode. The second electrode is provided on the first insulating portion. The second insulating portion is provided around the second electrode along a first plane perpendicular to a first direction. The second insulating portion contacts the second electrode. The first dielectric portion is provided between the first and second insulating portions. At least a portion of the first dielectric portion contacts the second electrode and is positioned around the second electrode along the first plane. A distance between a lower end of the second electrode and a first interface between the first dielectric portion and the second insulating portion is less than a distance between the first interface and an upper end of the second electrode.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: Yoshihiko Fuji, Ryohei Nega, Tatsuya Ohguro, Takanobu Kamakura
  • Patent number: 11916027
    Abstract: According to one embodiment, an isolator includes first and second electrodes, first and second insulating portions, and a first dielectric portion. The first insulating portion is provided on the first electrode. The second electrode is provided on the first insulating portion. The second insulating portion is provided around the second electrode along a first plane perpendicular to a first direction. The second insulating portion contacts the second electrode. The first dielectric portion is provided between the first and second insulating portions. At least a portion of the first dielectric portion contacts the second electrode and is positioned around the second electrode along the first plane. A distance between a lower end of the second electrode and a first interface between the first dielectric portion and the second insulating portion is less than a distance between the first interface and an upper end of the second electrode.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: February 27, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yoshihiko Fuji, Ryohei Nega, Tatsuya Ohguro, Takanobu Kamakura
  • Publication number: 20230378243
    Abstract: An isolator includes a first electrode; a first insulating portion on the first electrode; a second electrode on the first insulating portion; a second insulating portion around the second electrode; and a first dielectric portion on the second electrode and the second insulating portion. The second insulating portion is provided along a first plane perpendicular to a first direction from the first electrode toward the second electrode. The second electrode including a bottom surface facing the first insulating portion, an upper surface facing the first dielectric portion, a first side surface connected to the bottom surface, and a second side surface connected to the upper surface and the first side surface. The upper surface is wider than the bottom surface in a second direction along the first plane. The first side surface is tilted with respect to the bottom surface and the second side surface.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira ISHIGURO, Ryohei NEGA, Yoshihiko FUJI
  • Patent number: 11756986
    Abstract: An isolator includes a first electrode; a first insulating portion on the first electrode; a second electrode on the first insulating portion; a second insulating portion around the second electrode; and a first dielectric portion on the second electrode and the second insulating portion. The second insulating portion is provided along a first plane perpendicular to a first direction from the first electrode toward the second electrode. The second electrode including a bottom surface facing the first insulating portion, an upper surface facing the first dielectric portion, a first side surface connected to the bottom surface, and a second side surface connected to the upper surface and the first side surface. The upper surface is wider than the bottom surface in a second direction along the first plane. The first side surface is tilted with respect to the bottom surface and the second side surface.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: September 12, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Akira Ishiguro, Ryohei Nega, Yoshihiko Fuji
  • Publication number: 20220173208
    Abstract: An isolator includes a first electrode; a first insulating portion on the first electrode; a second electrode on the first insulating portion; a second insulating portion around the second electrode; and a first dielectric portion on the second electrode and the second insulating portion. The second insulating portion is provided along a first plane perpendicular to a first direction from the first electrode toward the second electrode. The second electrode including a bottom surface facing the first insulating portion, an upper surface facing the first dielectric portion, a first side surface connected to the bottom surface, and a second side surface connected to the upper surface and the first side surface. The upper surface is wider than the bottom surface in a second direction along the first plane. The first side surface is tilted with respect to the bottom surface and the second side surface.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 2, 2022
    Inventors: Akira Ishiguro, Ryohei Nega, Yoshihiko Fuji
  • Patent number: 11296185
    Abstract: An isolator includes a first electrode; a first insulating portion on the first electrode; a second electrode on the first insulating portion; a second insulating portion around the second electrode; and a first dielectric portion on the second electrode and the second insulating portion. The second insulating portion is provided along a first plane perpendicular to a first direction from the first electrode toward the second electrode. The second electrode including a bottom surface facing the first insulating portion, an upper surface facing the first dielectric portion, a first side surface connected to the bottom surface, and a second side surface connected to the upper surface and the first side surface. The upper surface is wider than the bottom surface in a second direction along the first plane. The first side surface is tilted with respect to the bottom surface and the second side surface.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: April 5, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira Ishiguro, Ryohei Nega, Yoshihiko Fuji
  • Publication number: 20210296427
    Abstract: An isolator includes a first electrode; a first insulating portion on the first electrode; a second electrode on the first insulating portion; a second insulating portion around the second electrode; and a first dielectric portion on the second electrode and the second insulating portion. The second insulating portion is provided along a first plane perpendicular to a first direction from the first electrode toward the second electrode. The second electrode including a bottom surface facing the first insulating portion, an upper surface facing the first dielectric portion, a first side surface connected to the bottom surface, and a second side surface connected to the upper surface and the first side surface. The upper surface is wider than the bottom surface in a second direction along the first plane. The first side surface is tilted with respect to the bottom surface and the second side surface.
    Type: Application
    Filed: September 8, 2020
    Publication date: September 23, 2021
    Inventors: Akira Ishiguro, Ryohei Nega, Yoshihiko Fuji
  • Publication number: 20210296043
    Abstract: An isolator includes a substrate; a first planar coil provided above the substrate and along a surface of the substrate; a first insulating portion on the first planar coil; a second planar coil on the first insulating portion; and a metal layer above the first insulating portion. The first planar coil, the second planar coil, and the metal layer are arranged in a first direction perpendicular to the surface of the substrate. The first planar coil and the second planar coil each having a center and an outer perimeter in a second direction along the surface of the substrate. A distance in the second direction from the center of the first planar coil to the outer perimeter of the first planar coil is less than a distance in the second direction from the center of the second planar coil to the outer perimeter of the second planar coil.
    Type: Application
    Filed: September 9, 2020
    Publication date: September 23, 2021
    Inventors: Ryohei NEGA, Yoshihiko FUJI, Tatsuya OHGURO, Takanobu KAMAKURA
  • Publication number: 20210296265
    Abstract: According to one embodiment, an isolator includes first and second electrodes, first and second insulating portions, and a first dielectric portion. The first insulating portion is provided on the first electrode. The second electrode is provided on the first insulating portion. The second insulating portion is provided around the second electrode along a first plane perpendicular to a first direction. The second insulating portion contacts the second electrode. The first dielectric portion is provided between the first and second insulating portions. At least a portion of the first dielectric portion contacts the second electrode and is positioned around the second electrode along the first plane. A distance between a lower end of the second electrode and a first interface between the first dielectric portion and the second insulating portion is less than a distance between the first interface and an upper end of the second electrode.
    Type: Application
    Filed: September 10, 2020
    Publication date: September 23, 2021
    Inventors: Yoshihiko Fuji, Ryohei Nega, Tatsuya Ohguro, Takanobu Kamakura
  • Patent number: 10135337
    Abstract: Provided is a semiconductor device including a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: November 20, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryohei Nega, Yoshinao Miura
  • Patent number: 9985108
    Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1-x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0<x?0.2 is satisfied. Also, both of a concentration of a p-type impurity and a concentration of an n-type impurity in the AlGaN layer AGN are 1×1016 cm?3 or lower. In this example, the p-type impurity is exemplified by, for example, Be, C, and Mg, and the n-type impurity is exemplified by Si, S, and Se. Also, the Al electrodes DE and SE are connected to the AlGaN layer AGN. Because a composition ratio of Al is limited to the above-mentioned range, the Al electrodes DE and SE are brought into ohmic contact with the AlGaN layer AGN.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: May 29, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Masaaki Kanazawa, Yasuhiro Okamoto, Takashi Inoue, Hironobu Miyamoto, Ryohei Nega
  • Publication number: 20170222559
    Abstract: Provided is a semiconductor device including a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Inventors: Ryohei Nega, Yoshinao Miura
  • Patent number: 9667147
    Abstract: Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 30, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryohei Nega, Yoshinao Miura
  • Patent number: 9536978
    Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: January 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Ryohei Nega, Masaaki Kanazawa, Takashi Inoue
  • Publication number: 20160190930
    Abstract: Provided is a semiconductor device including: a DC/DC converter circuit, wherein the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected town input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Inventors: Ryohei Nega, Yoshinao Miura
  • Publication number: 20160133715
    Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Takashi Inoue, Tatsuo Nakayama, Ryohei Nega, Masaaki Kanazawa, Hironobu Miyamoto
  • Patent number: 9324851
    Abstract: A semiconductor device including a DC/DC converter circuit, in which the DC/DC converter circuit includes a transistor of a normally-off type, having a first drain electrode connected to an input terminal and a first source electrode connected to an output terminal, which is formed in a first compound semiconductor substrate having a two-dimensional electron gas layer, and a transistor having a second drain electrode connected to the first source electrode and a grounded second source electrode.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: April 26, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryohei Nega, Yoshinao Miura
  • Patent number: 9269803
    Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: February 23, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Takashi Inoue, Tatsuo Nakayama, Ryohei Nega, Masaaki Kanazawa, Hironobu Miyamoto
  • Publication number: 20150041821
    Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1?x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0<X?0.2 is satisfied. Also, both of a concentration of a p-type impurity and a concentration of an n-type impurity in the AlGaN layer AGN are 1×1016 cm?3 or lower. In this example, the p-type impurity is exemplified by, for example, Be, C, and Mg, and the n-type impurity is exemplified by Si, S, and Se. Also, the Al electrodes DE and SE are connected to the AlGaN layer AGN. Because a composition ratio of Al is limited to the above-mentioned range, the Al electrodes DE and SE are brought into ohmic contact with the AlGaN layer AGN.
    Type: Application
    Filed: July 14, 2014
    Publication date: February 12, 2015
    Inventors: Tatsuo Nakayama, Masaaki Kanazawa, Yasuhiro Okamoto, Takashi Inoue, Hironobu Miyamoto, Ryohei Nega
  • Publication number: 20140264274
    Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 18, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Ryohei NEGA, Masaaki KANAZAWA, Takashi INOUE