Abstract: A receiving device includes an equalization processor including multiple delay equalizers. The equalization processor is configured to: obtain a first error between an output of one specific tap in the multiple delay equalizers and a predetermined reference value, and calculate a first weight with which the first error is minimized; cause a calculation result of the first weight to be reflected in all taps in the multiple delay equalizers except the specific tap, obtain a second error between outputs of all taps in the multiple delay equalizers and the predetermined reference value, and calculate a second weight with which the second error is minimized; and update coefficients of all taps in the multiple delay equalizers at the same timing using the calculation result of the first weight and a calculation result of the second weight, and calculate an output of the equalization processor.

Abstract: A receiving device includes an equalization processor including multiple delay equalizers. The equalization processor is configured to: obtain a first error between an output of one specific tap in the multiple delay equalizers and a predetermined reference value, and calculate a first weight with which the first error is minimized; cause a calculation result of the first weight to be reflected in all taps in the multiple delay equalizers except the specific tap, obtain a second error between outputs of all taps in the multiple delay equalizers and the predetermined reference value, and calculate a second weight with which the second error is minimized; and update coefficients of all taps in the multiple delay equalizers at the same timing using the calculation result of the first weight and a calculation result of the second weight, and calculate an output of the equalization processor.