Abstract: A packet processing apparatus includes a memory configured to store, for each time slot number, switching information for switching output of a packet of each packet type, a counter configured to count the time slot number, an output control circuit configured to control the output, based on the switching information that corresponds to the time slot number currently counted, a transmitter configured to transmit a control packet for resetting the time slot number currently counted in each packet processing apparatus in a set path, in a predetermined direction of the set path in accordance with a predetermined timing, and a reset circuit configured to, in response to a start of a transmission of the control packet, reset the time slot number currently counted and restart a count operation of the counter.

Abstract: A packet processing device is implemented in a network that transmits priority packets and non-priority packets having a lower priority than the priority packets. The packet processing device includes: a packet storage, a gate, a controller, a detector, a generator, and a transmitter. The packet storage stores non-priority packets. The gate is provided on an output side of the packet storage. The controller controls the gate. The detector detects a transmission pattern of the priority packets. The generator generates, based on the transmission pattern of the priority packets, a gate control signal for controlling a gate of a packet processing device implemented in another node. The transmitter transmits the gate control signal to a destination of the priority packets.

Abstract: A packet processing device is implemented in a network that transmits priority packets and non-priority packets having a lower priority than the priority packets. The packet processing device includes: a packet storage, a gate, a controller, a detector, a generator, and a transmitter. The packet storage stores non-priority packets. The gate is provided on an output side of the packet storage. The controller controls the gate. The detector detects a transmission pattern of the priority packets. The generator generates, based on the transmission pattern of the priority packets, a gate control signal for controlling a gate of a packet processing device implemented in another node. The transmitter transmits the gate control signal to a destination of the priority packets.

Abstract: A communication system includes: a plurality of active paths on which a plurality of signals set with priorities are transmitted by a plurality of time-division slots; a backup path shared by the plurality of active paths; and a controller configured to control, based on the priorities, allocation of any of the plurality of signals which are allocated to any of the plurality of time-division slots and transmitted on any of the plurality of active paths, to a plurality of time-division slots on the backup path.