Patents by Inventor Ryoichi Furukawa

Ryoichi Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170272716
    Abstract: A projection apparatus includes an input unit configured to input an image signal, a projection unit configured to project an image corresponding to the image signal, an attitude sensor configured to detect an attitude around a projection optical axis of the projection unit in which the projection apparatus is installed, and a projection control unit configured to project, when the attitude detected by the attitude sensor falls within a predetermined range, the image under a first projection condition, and project, when the attitude detected by the attitude sensor falls outside the predetermined range, the image under a second projection condition different from the first projection condition.
    Type: Application
    Filed: December 16, 2016
    Publication date: September 21, 2017
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Atsushi NAKAGAWA, Ryoichi FURUKAWA
  • Patent number: 7758265
    Abstract: A printing apparatus has an apparatus body including a platen roller, a thermal head, a storage in which a ribbon cartridge is stored exchangeably through an opening, and a cover of the apparatus body that covers the opening so as to be opened and closed. A gap is secured between an edge portion of the cover provided for the apparatus body in a state in which the cover is fitted onto the apparatus body to close the apparatus body and an edge portion of the opening of the storage. The gap is a slot for inserting an optical disk in its upright position to the apparatus body.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: July 20, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ryoichi Furukawa, Katsuyuki Matsuo
  • Patent number: 7655993
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: February 2, 2010
    Assignee: Renesas Technology Corporation
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
  • Patent number: 7513706
    Abstract: A main body has a receiving section, which contains an ink ribbon cassette holding an ink ribbon, together with an optical disk. The ink ribbon and the optical disk are fed by a platen roller, and printing is performed on the optical disk through a thermal head. The optical disk is inserted from an insertion port at a side of the main body parallel to the feed direction of the ink ribbon. When the optical disk is inserted from an ejection port in a direction orthogonal to the fed direction of the ink ribbon, an insertion-prevention member prevents the insertion of the optical disk.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: April 7, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Satoshi Kimura, Yoshiaki Mochizuki, Katsuyuki Matsuo, Ryoichi Furukawa, Chihiro Fujishima
  • Publication number: 20070231045
    Abstract: A printing apparatus has an apparatus body including a platen roller, a thermal head, a storage in which a ribbon cartridge is stored exchangeably through an opening, and a cover of the apparatus body that covers the opening so as to be opened and closed. A gap is secured between an edge portion of the cover provided for the apparatus body in a state in which the cover is fitted onto the apparatus body to close the apparatus body and an edge portion of the opening of the storage. The gap is a slot for inserting an optical disk in its upright position to the apparatus body.
    Type: Application
    Filed: March 23, 2007
    Publication date: October 4, 2007
    Applicant: Casio Computer Co., Ltd.
    Inventors: Ryoichi Furukawa, Katsuyuki Matsuo
  • Publication number: 20070187764
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Application
    Filed: April 23, 2007
    Publication date: August 16, 2007
    Inventors: RYOICHI FURUKAWA, Satoshi Sakai, Satoshi Yamamoto
  • Patent number: 7217607
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: May 15, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
  • Patent number: 7186604
    Abstract: After forming a silicon oxide film 9 on the surface of a region A of a semiconductor substrate 1, a high dielectric constant insulating film 10, a silicon film, a silicon oxide film 14 are successively deposited over the semiconductor substrate 1, and they are patterned to leave the silicon oxide film 14 in regions for forming gate electrodes. Then, after fabricating silicon films 13n and 13p by using the patterned silicon oxide film 14 as a mask, when removing the silicon oxide film 14, etching is performed under the condition where the etching selectivity of the silicon oxide film 14 to the high dielectric constant insulating film 10 becomes large, thereby leaving the high dielectric constant insulating film 10 also to portions below the end of the gate electrodes (13n, 13p). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: March 6, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Sakai, Satoshi Yamamoto, Atsushi Hiraiwa, Ryoichi Furukawa
  • Publication number: 20060121740
    Abstract: After forming a silicon oxide film 9 on the surface of a region A of a semiconductor substrate 1, a high dielectric constant insulating film 10, a silicon film, a silicon oxide film 14 are successively deposited over the semiconductor substrate 1, and they are patterned to leave the silicon oxide film 14 in regions for forming gate electrodes. Then, after fabricating silicon films 13n and 13p by using the patterned silicon oxide film 14 as a mask, when removing the silicon oxide film 14, etching is performed under the condition where the etching selectivity of the silicon oxide film 14 to the high dielectric constant insulating film 10 becomes large, thereby leaving the high dielectric constant insulating film 10 also to portions below the end of the gate electrodes (13n, 13p). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.
    Type: Application
    Filed: August 15, 2002
    Publication date: June 8, 2006
    Inventors: Satoshi Sakai, Satoshi Yamamoto, Atsushi Hiraiwa, Ryoichi Furukawa
  • Publication number: 20060078366
    Abstract: A main body has a receiving section, which contains an ink ribbon cassette holding an ink ribbon, together with an optical disk. The ink ribbon and the optical disk are fed by a platen roller, and printing is performed on the optical disk through a thermal head. The optical disk is inserted from an insertion port at a side of the main body parallel to the feed direction of the ink ribbon. When the optical disk is inserted from an ejection port in a direction orthogonal to the fed direction of the ink ribbon, an insertion-prevention member prevents the insertion of the optical disk.
    Type: Application
    Filed: October 12, 2005
    Publication date: April 13, 2006
    Applicant: Casio Computer Co., Ltd.
    Inventors: Satoshi Kimura, Yoshiaki Mochizuki, Katsuyuki Matsuo, Ryoichi Furukawa, Chihiro Fujishima
  • Patent number: 6909133
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
  • Publication number: 20050077548
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Application
    Filed: October 20, 2004
    Publication date: April 14, 2005
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
  • Patent number: 6764916
    Abstract: A manufacturing method for a semiconductor device, including forming on or above a semiconductor substrate a silicon film a surface of which has a first polycrystalline silicon film with mushroom or hemisphere-shaped crystal grains, and forming a Ta2O5 film on the silicon film at a pressure of 40 Pa or lower and at a temperature of 480° C. or lower, using a gas obtained by vaporizing Ta(OC2H5)5 as a tantalum source gas.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: July 20, 2004
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Ryoichi Furukawa, Tadanori Yoshida, Masayuki Tsuneda, Yasuhiro Inokuchi, Satoru Tagami
  • Publication number: 20040106289
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Application
    Filed: November 4, 2003
    Publication date: June 3, 2004
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
  • Patent number: 6660597
    Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: December 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto
  • Publication number: 20030092233
    Abstract: In a process of forming MISFETs mutually different in thickness of the gate insulating film on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs (Qn1 and Qp1) constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs (Qn2 and Qp2) constituting an I/O circuit is comprised of a laminated film of a silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matters and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 15, 2003
    Inventors: Ryoichi Furukawa, Satoshi Sakai, Satoshi Yamamoto