Abstract: A buffer circuit section receives an input clock, and outputs an output clock by wave-shaping the input clock, a measurement circuit section measures a first pulse width at a first potential level of the output clock and a second pulse width at a second potential level of the output clock, and an adjustment circuit section adjusts a ratio between the first pulse width and the second pulse width by varying a drive capability of the buffer circuit section on the basis of the measurement result of the measurement circuit section.

Abstract: For each of a plurality of delayed phases, one of the plurality of delayed phases being the same as a phase of a reference clock and the others of the plurality of delayed phases delayed with respect to the phase of the reference clock, test parallel data transmitted in synchronism with the reference clock is received in synchronism with a delayed clock having the delayed phase and an adjacent delayed clock having a delayed phase adjacent to the delayed phase of the delayed clock, respectively; and a phase range containing a delayed phase with which the test parallel data has been received correctly and for which the result of the comparison indicates a match is determined from among the plurality of delayed phases; and the phase of a receive clock to be used for reception of parallel data is determined from the determined phase range.

Abstract: For each of a plurality of delayed phases, one of the plurality of delayed phases being the same as a phase of a reference clock and the others of the plurality of delayed phases delayed with respect to the phase of the reference clock, test parallel data transmitted in synchronism with the reference clock is received in synchronism with a delayed clock having the delayed phase and an adjacent delayed clock having a delayed phase adjacent to the delayed phase of the delayed clock, respectively; and a phase range containing a delayed phase with which the test parallel data has been received correctly and for which the result of the comparison indicates a match is determined from among the plurality of delayed phases; and the phase of a receive clock to be used for reception of parallel data is determined from the determined phase range.

Abstract: A buffer circuit section receives an input clock, and outputs an output clock by wave-shaping the input clock, a measurement circuit section measures a first pulse width at a first potential level of the output clock and a second pulse width at a second potential level of the output clock, and an adjustment circuit section adjusts a ratio between the first pulse width and the second pulse width by varying a drive capability of the buffer circuit section on the basis of the measurement result of the measurement circuit section.

Abstract: A integrated circuit include: a first selection circuit selecting first data from input-data or scan-data, scan-data being for performing a diagnosis of a combinational circuit, input-data being received from a combinational circuit; a first latch circuit holding first data as first output-data in accordance with a first signal; a second latch circuit holding first output-data as second output-data in accordance with which of the first signal and a second signal, the second signal being used to force the second latch circuit to hold first output-data; a third latch circuit holding first output-data as third output-data in accordance with which of the first signal and a third signal, the third signal being used to force the third latch circuit to hold first output-data; and a second selection circuit selecting second data from among the data which include second output-data and third output-data.

Abstract: A integrated circuit include: a first selection circuit selecting first data from input-data or scan-data, scan-data being for performing a diagnosis of a combinational circuit, input-data being received from a combinational circuit; a first latch circuit holding first data as first output-data in accordance with a first signal; a second latch circuit holding first output-data as second output-data in accordance with which of the first signal and a second signal, the second signal being used to force the second latch circuit to hold first output-data; a third latch circuit holding first output-data as third output-data in accordance with which of the first signal and a third signal, the third signal being used to force the third latch circuit to hold first output-data; and a second selection circuit selecting second data from among the data which include second output-data and third output-data.