Patents by Inventor RYOICHI KAIZU

RYOICHI KAIZU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240003851
    Abstract: A power module comprises an element and an insulated circuit board having a laminated portion. The laminated portion includes a first metal layer, a bonding layer interposed between an element and the first metal layer, a second metal layer, and a resin layer interposed between the first metal layer and the second metal layer. The insulated circuit board has a pair of laminated portions provided so as to sandwich the element. The laminated portions are configured so that ultrasonic pulses emitted from an outside of the second metal layer toward the element have the following relationship of detection time periods. A time period in which the ultrasonic pulse travels two roundtrips in the second metal layer is longer than a time period in which the ultrasonic pulse travels one roundtrip in a range from the second metal layer to the element.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 4, 2024
    Inventors: Ryoichi KAIZU, Yuki INABA, Tomomi OKUMURA, Toshifumi HOSONO
  • Patent number: 11710709
    Abstract: A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: July 25, 2023
    Assignee: DENSO CORPORATION
    Inventors: Ryoichi Kaizu, Takumi Nomura, Tetsuto Yamagishi, Yuki Inaba, Yoshitsugu Sakamoto
  • Publication number: 20230130647
    Abstract: A semiconductor device includes a semiconductor chip having first and second main electrodes disposed on opposite surfaces of a silicon carbide substrate, first and second heat dissipation members disposed so as to sandwich the semiconductor chip, and joining members disposed between the first main electrode and the first heat dissipation member and between the second main electrode and the second heat dissipation member. At least one of the joining members is made of a lead-free solder having an alloy composition that contains 3.2 to 3.8 mass % Ag, 0.6 to 0.8 mass % Cu, 0.01 to 0.2 mass % Ni, x mass % Sb, y mass % Bi, 0.001 to 0.3 mass % Co, 0.001 to 0.2 mass % P, and a balance of Sn, where x and y satisfy relational expressions of x+2y?11 mass %, x+14y?42 mass %, and x?5.1 mass %.
    Type: Application
    Filed: December 27, 2022
    Publication date: April 27, 2023
    Inventors: Tetsuto YAMAGISHI, Yoshitsugu SAKAMOTO, Ryoichi KAIZU, Yuki INABA, Hiroki YOSHIKAWA
  • Publication number: 20210233871
    Abstract: A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: RYOICHI KAIZU, TAKUMI NOMURA, TETSUTO YAMAGISHI, YUKI INABA, YOSHITSUGU SAKAMOTO