Patents by Inventor Ryoichi Kimizuka
Ryoichi Kimizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180298515Abstract: Instead of the renewal or purification of copper sulfate plating solutions performed based on the increase of defective products as an ex post facto measure or the empirical determination, a technique capable of managing copper sulfate plating solutions by assessing the aging of the copper sulfate plating solutions in an objective manner is provided. A method for managing a copper sulfate plating solution used for performing copper sulfate plating for a material to be plated, the method containing: measuring a concentration of impurities in the copper sulfate plating solution; and assessing aging of the copper sulfate plating solution from the concentration of the impurities.Type: ApplicationFiled: April 27, 2015Publication date: October 18, 2018Applicant: JCU CORPORATIONInventors: Tetsuro EDA, Hisayuki TODA, Kazuki KISHIMOTO, Yasuko TAKAYA, Ryoichi KIMIZUKA
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Patent number: 9321741Abstract: Provided is a copper plating technique that enables the filling of high aspect-ratio via-holes and through-holes in semiconductor substrates such as silicon substrates, organic material substrates or ceramic substrates. The disclosed technique involves a tertiary amine compound, which is obtained by reacting a heterocyclic compound with the epoxy group of a glycidyl ether group of a compound that has three or more glycidyl ether groups, and a quaternary amine compound thereof, as well as a copper plating additive, a copper plating bath, and a copper plating method employing the compounds.Type: GrantFiled: April 30, 2010Date of Patent: April 26, 2016Assignee: JCU CORPORATIONInventors: Hiroki Yasuda, Ryoichi Kimizuka, Tatsuji Takasu, Takuro Sato, Hiroshi Ishizuka, Yasuhiro Ogo, Yuto Oyama, Yu Tonooka, Mikiko Kosaka, Aya Shimomura, Yumiko Shimizu
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Publication number: 20130043137Abstract: Provided is a copper plating technique that enables the filling of high aspect-ratio via-holes and through-holes in semiconductor substrates such as silicon substrates, organic material substrates or ceramic substrates. The disclosed technique involves a tertiary amine compound, which is obtained by reacting a heterocyclic compound with the epoxy group of a glycidyl ether group of a compound that has three or more glycidyl ether groups, and a quaternary amine compound thereof, as well as a copper plating additive, a copper plating bath, and a copper plating method employing the compounds.Type: ApplicationFiled: April 30, 2010Publication date: February 21, 2013Applicant: JCU CORPORATIONInventors: Hiroki Yasuda, Ryoichi Kimizuka, Tatsuji Takasu, Takuro Sato, Hiroshi Ishizuka, Yasuhiro Ogo, Yuto Oyama, Yu Tonooka, Mikiko Kosaka, Aya Shimomura, Yumiko Shimizu
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Patent number: 7553400Abstract: A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.Type: GrantFiled: December 21, 2004Date of Patent: June 30, 2009Assignees: Ebara Corporation, International Business Machines Corporation (IBM)Inventors: Mizuki Nagai, Hiroyuki Kanda, Keiichi Kurashina, Satoru Yamamoto, Ryoichi Kimizuka, Hariklia Deligianni, Brett Baker, Keith Kwietniak, Panayotis Andricacos, Phillipe Vereecken
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Publication number: 20080264798Abstract: An acid copper plating solution and plating method are disclosed. The acid copper plating solution comprises copper ions, an organic acid or an inorganic acid, chloride ions, high molecular weight surfactant which controls the electrodeposition reaction, and a sulfur-containing saturated organic compound which promotes the electrocoating rate, wherein the high molecular weight surfactant comprises two or more types with different hydrophobicities. The plating method is a method for forming a plating film on a conductor layer, which is formed on at least a part of a structural object having a concave-convex pattern on a semiconductor substrate, and comprises providing a cathode potential to the conductor layer and supplying a plating solution which electrically connects an anode with the conductor layer, wherein the plating solution contains 25-75 g/l of copper ion and 0.4 mol/l of an organic acid or inorganic acid and an electric resistor is installed between the conductor layer and the anode.Type: ApplicationFiled: June 13, 2008Publication date: October 30, 2008Applicants: EBARA CORPORATION, EBARA-UDYLITE CO., LTD.Inventors: Tsutomu NAKADA, Tsuyoshi Sahoda, Koji Mishima, Ryoichi Kimizuka, Takeshi Kobayashi
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Publication number: 20080087549Abstract: An additive for copper plating comprising, as an effective ingredient, a nitrogen-containing biphenyl derivative represented by the following formula (I): [wherein X represents a group selected from the following groups (II)-(VII): and Y represents a lower alkyl group, lower alkoxy group, nitro group, amino group, sulfonyl group, cyano group, carbonyl group, 1-pyridyl group, or the formula (VIII): (wherein R? represents a lower alkyl group)], a copper plating solution formed by adding the additive for copper plating to a copper plating solution containing a copper ion ingredient and an anion ingredient, and a method of manufacturing on an electronic circuit substrate having a fine copper wiring circuit, which comprises electroplating in the copper plating solution using as the cathode an electronic circuit substrate in which fine microholes or microgrooves in the shape of an electronic circuit are formed on the surface.Type: ApplicationFiled: August 18, 2004Publication date: April 17, 2008Applicant: EBARA-UDYLITE CO.,LTD.Inventors: Hiroshi Ishizuka, Nobuo Sakagawa, Ryoichi Kimizuka, Wei-ping Dow
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Publication number: 20070102285Abstract: The concentration of a leveler in a plating liquid that is used by a plating apparatus for filling metal such as copper in interconnection trenches and holes defined in the surface of a semiconductor substrate or the like is determined based on a peak area (Ar value) in a peel-off region of the plating liquid measured according to a CV or CVS process.Type: ApplicationFiled: December 22, 2006Publication date: May 10, 2007Inventors: Yasushi Isayama, Hiroyuki Ueyama, Hiroyuki Kaneko, Junitsu Yamakawa, Akihisa Hongo, Ryoichi Kimizuka, Megumi Maruyama
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Patent number: 7172683Abstract: The concentration of a leveler in a plating liquid that is used by a plating apparatus for filling metal such as copper in interconnection trenches and holes defined in the surface of a semiconductor substrate or the like is determined based on a peak area (Ar value) in a peel-off region of the plating liquid measured according to a CV or CVS process.Type: GrantFiled: July 28, 2003Date of Patent: February 6, 2007Assignee: Ebara CorporationInventors: Yasushi Isayama, Hiroyuki Ueyama, Hiroyuki Kaneko, Junitsu Yamakawa, Akihisa Hongo, Ryoichi Kimizuka, Megumi Maruyama
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Publication number: 20060144714Abstract: A method and apparatus plate a substrate to form wiring by efficiently filling a fine recess formed in a semiconductor substrate with plating metal without a void or contamination. The plating of the substrate to fill a wiring recess formed in the semiconductor substrate with plating metal includes performing an electroless plating process of forming an initial layer on the substrate, and performing an electrolytic plating process of filling the wiring recess with the plating metal, while the initial layer serves as a feeding layer.Type: ApplicationFiled: February 24, 2006Publication date: July 6, 2006Inventors: Akihisa Hongo, Naoaki Ogure, Hiroaki Inous, Satoshi Sendai, Tetsuma Ikegami, Koji Mishima, Shuichi Okuyama, Mizuki Nagai, Ryoichi Kimizuka, Megumi Maruyama
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Patent number: 7033463Abstract: A method and apparatus plate a substrate to form wiring by efficiently filling a fine recess formed in a semiconductor substrate with plating metal without a void or contamination. The plating of the substrate to fill a wiring recess formed in the semiconductor substrate with plating metal includes performing an electroless plating process of forming an initial layer on the substrate, and performing an electrolytic plating process of filling the wiring recess with the plating metal, while the initial layer serves as a feeding layer.Type: GrantFiled: August 11, 1999Date of Patent: April 25, 2006Assignee: Ebara CorporationInventors: Akihisa Hongo, Naoaki Ogure, Hiroaki Inoue, Satoshi Sendai, Tetsuma Ikegami, Koji Mishima, Shuichi Okuyama, Mizuki Nagai, Ryoichi Kimizuka, Megumi Maruyama
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Publication number: 20050282384Abstract: The present invention provides a method for forming a protective film selectively on metal interconnects, such as copper interconnects, of a substrate having an embedded interconnect structure, without causing the problem of contamination of the interconnects with an-alkali metal. The method for forming a protective film according to the present invention comprises: providing a substrate having embedded interconnects formed in a surface of the substrate; and bringing the surface of the substrate into contact with an electroless plating bath, thereby forming a protective film having a film thickness of 0.1 to 500 nm selectively on the exposed surface of the embedded interconnects; wherein the electroless plating bath contains cobalt ions, phosphinate ions and a complexing agent, uses cobalt phosphinate as a main supply source of the cobalt ions and the phosphinate ions, and does not substantially contain alkali metal ions.Type: ApplicationFiled: June 17, 2004Publication date: December 22, 2005Inventors: Hidemi Nawafune, Kensuke Akamatsu, Katashige Matsuda, Akira Fukunaga, Ryoichi Kimizuka, Moriji Matsumoto
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Publication number: 20050241946Abstract: A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.Type: ApplicationFiled: December 21, 2004Publication date: November 3, 2005Inventors: Mizuki Nagai, Hiroyuki Kanda, Keiichi Kurashina, Satoru Yamamoto, Ryoichi Kimizuka, Hariklia Deligianni, Brett Baker, Keith Kwietniak, Panayotis Andricacos, Philippe Vereecken
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Patent number: 6908534Abstract: A method and apparatus for plating a substrate is provided, wherein fine pits formed in the substrate, such as fine channels for wiring, are filled with a copper, copper alloy, or other material with low electrical resistance. The method is performed on a wafer W having fine pits (10) to fill the fine pits with a metal (13) and includes performing a first plating process (11) by immersing the wafer in a first plating solution having a composition superior in throwing power; and performing a second plating process (12) by immersing the substrate in a second plating solution having a composition superior in leveling ability.Type: GrantFiled: December 18, 2001Date of Patent: June 21, 2005Assignee: Ebara CorporationInventors: Akihisa Hongo, Mizuki Nagai, Kanji Ohno, Ryoichi Kimizuka, Megumi Maruyama
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Publication number: 20050126919Abstract: A copper plating film has a lower chlorine ion content. Circuit wiring of high electromigration resistance is formed by electroplating. In a method of copper plating using a leveler containing a nitrogen-containing high molecular compound, the leveler is dechlorinated prior to its use for plating. A plating apparatus has a tank for preparing a plating solution, a device for dechlorinating a leveler, a leveler supply station for supplying the dechlorinated leveler to the tank and a plating station. A method of forming fine circuit wiring includes forming a circuit with a phosphorus-doped copper plating layer on a substrate for an electronic circuit having a fine circuit pattern, a barrier layer and any necessary seed layer formed thereon.Type: ApplicationFiled: November 4, 2004Publication date: June 16, 2005Inventors: Makoto Kubota, Tsuyoshi Sahoda, Tsutomu Nakada, Koji Mishima, Ryoichi Kimizuka
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Publication number: 20050098439Abstract: A method and apparatus for plating a substrate is provided, wherein fine pits formed in the substrate, such as fine channels for wiring, are filled with a copper, copper alloy, or other material with low electrical resistance. The method is performed on a wafer W having fine pits (10) to fill the fine pits with a metal (13) and includes performing a first plating process (11) by immersing the wafer in a first plating solution having a composition superior in throwing power; and performing a second plating process (12) by immersing the substrate in a second plating solution having a composition superior in leveling ability.Type: ApplicationFiled: December 10, 2004Publication date: May 12, 2005Inventors: Akihisa Hongo, Mizuki Nagai, Kanji Ohno, Ryoichi Kimizuka, Megumi Maruyama
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Publication number: 20050072683Abstract: An acid copper plating solution comprises copper ions, an organic acid or an inorganic acid, chloride ions, a high molecular weight surfactant that controls the electrodeposition reaction, and a sulfur-containing saturated organic compound that promotes the electrocoating rate. The high molecular weight surfactant comprises two or more types of surfactants with different hydrophobicities. The plating solution is used for forming a plating film on a conductor layer.Type: ApplicationFiled: April 2, 2004Publication date: April 7, 2005Applicants: EBARA CORPORATION, EBARA-UDYLITE CO., LTD.Inventors: Tsutomu Nakada, Tsuyoshi Sahoda, Koji Mishima, Ryoichi Kimizuka, Takeshi Kobayashi
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Publication number: 20050045486Abstract: The present invention provides a plating method which can embed copper in interconnect recesses, such as vias and interconnect trenches, having an opening width or size of several tens of ?m and an aspect ratio of at least 1.5. The plating method comprises: providing a substrate having interconnect recesses, whose surfaces are covered with a conductive layer, formed in a surface of the substrate; bringing the surface of the substrate into contact with a plating solution containing copper ions, an organic or inorganic acid, chloride ions, a polymeric surfactant for suppressing electrodeposition, a sulfur-containing saturated organic compound for promoting the growth of a plated film, and a nitrogen-containing polymer for flattening a surface of the plated film; and applying a voltage between the conductive layer and an anode immersed in the plating solution.Type: ApplicationFiled: July 7, 2004Publication date: March 3, 2005Inventors: Tsuyoshi Sahoda, Tsutomu Nakada, Koji Mishima, Ryoichi Kimizuka
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Patent number: 6811658Abstract: A method and apparatus for forming interconnects embedding a metal such as copper (Cu) into recesses for interconnects formed on the surface of a substrate such as a semiconductor substrate. The method includes providing a substrate having fine recesses formed in the surface, subjecting the surface of the substrate to plating in a plating liquid, and subjecting the plated film formed on the surface of the substrate to electrolytic etching in an etching liquid.Type: GrantFiled: June 27, 2001Date of Patent: November 2, 2004Assignee: Ebara CorporationInventors: Akihisa Hongo, Naoki Matsuda, Kanji Ohno, Ryoichi Kimizuka
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Publication number: 20040200728Abstract: A method and apparatus for forming interconnects embedding a metal such as copper (Cu) into recesses for interconnects formed on the surface of a substrate such as a semiconductor substrate. The method includes providing a substrate having fine recesses formed in the surface, subjecting the surface of the substrate to plating in a plating liquid, and subjecting the plated film formed on the surface of the substrate to electrolytic etching in an etching liquid.Type: ApplicationFiled: May 4, 2004Publication date: October 14, 2004Inventors: Akihisa Hongo, Naoki Matsuda, Kanji Ohno, Ryoichi Kimizuka
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Patent number: 6800188Abstract: A copper plating bath comprising a reaction condensate of an amine compound and glycidyl ether and/or a quaternary ammonium derivative of this reaction condensate, and a plating method using this copper plating bath are disclosed. A copper plating bath capable of providing highly reliable copper plating on a substrate such as a silicone wafer semiconductor substrate or printed board having minute circuit patterns and small holes such as blind via-holes, through-holes, and the like, and a method of copper plating using the copper plating bath can be provided.Type: GrantFiled: May 9, 2002Date of Patent: October 5, 2004Assignees: Ebara-Udylite Co., Ltd., Ebara CorporationInventors: Hideki Hagiwara, Ryoichi Kimizuka, Yoshitaka Terashima, Megumi Maruyama, Takashi Miyake, Hiroshi Nagasawa, Tsuyoshi Sahoda, Seiji Iimura