Abstract: A process of epitaxially growing a semiconductor Si, Ge or SiGe single crystal layer on a semiconductor (Si or Ge) single crystal substrate, comprising the steps of: allowing a raw material gas (e.g., Si.sub.2 H.sub.6, GeH.sub.4) for the layer and a fluoride gas (e.g., Si.sub.2 F.sub.6, GeF.sub.4, BF) of at least one element selected from the group consisting of the semiconductor element of the layer and a dopant for the layer to simultaneously flow over the substrate; and applying an ultraviolet light to the substrate to decompose the gases by an ultraviolet light excitation reaction to deposit the layer on the surface of the substrate heated at a temperature of from 250.degree. to 400.degree. C.Prior to the epitaxial growth of the semiconductor layer, the substrate is cleaned by allowing the fluoride gas to flow over the substrate having a temperature of from a room temperature to 500.degree. C.

Abstract: In a conductive plug forming method, a conductor layer is formed on the main surface of an insulator layer, only in the vicinity of a plurality of adjacent via holes in which plugs are to be formed, the conductor layer having a periphery defining a boundary encompassing the plurality of adjacent via holes. The volume of the material of the conductor layer within the boundary is of a predetermined amount, ranging from a minimum volume approximately equal to, to a maximum volume approximately equal to two times the total interior volume of the via holes. An energy beam is irradiated on the conductor layer to melt the conductor layer, so that the melted conductor material of the conductor layer flows toward and into the via holes, thereby forming a conductive plug in each of the via holes and without leaving any conductor layer material on the main surface of the substrate.

Abstract: A planarization method includes the steps of forming a second layer on a first layer which has an alignment mark having a heat sink structure, where the second layer is made of a metal, and irradiating a pulse energy beam on the entire exposed surface of the second layer to planarize the second layer. The heat generated in the second layer on the alignment mark is released via the first layer so that substantially no melting of the second layer occurs on the alignment mark.

Abstract: A random layout of devices, or at least active regions of devices, is achieved in fabricating semiconductor integrated circuits based on SOI technology using an anti-reflecting film. Windows are opened in the anti-reflecting film at positions corresponding to preselected regions of the semiconductor layer in which corresponding devices are to be formed, thereby to expose at least the surface area of each preselected region corresponding to the active region of the device to be formed therein. For each window, an energy beam substantially uniformly irradiates the exposed surface area including a portion of the anti-reflecting film bordering the window, sufficiently to heat the semiconductor layer and recrystallize the region thereof corresponding to the exposed surface area to a single crystalline form, free of grain boundaries. Self-aligned single crystal regions thus are fabricated in the polycrystalline silicon layer at the respective predetermined device regions.

Abstract: A conducting link is disposed in an insulating layer of a semiconductor device in combination with a plurality of wirings of the device which are electrically separated from each other. The conducting link is selectively activated to provide the wirings with a conducting path, and is activatable by melting metal contained in the wirings by irradiating a portion of the wirings in the vicinity of the link with a shot of a pulse of laser beam. The link comprises a through hole or a trench disposed in the insulating layer depending on the structural configuration of the device. The method of fabricating and activating the conductive link is provided.

Abstract: A method for fabricating a semiconductor device with via holes, each having a width less than one micrometer and an aspect ratio more than one, assures proper filling of the via rolls with metal from a sputtered metal layer on an insulating layer having the via holes and formed on a semiconductor substrate by using a pulsed laser beam for planarization. The sputtered metal layer must be thick enough to provide the planarized metal layer with 0.5 micrometer thickness in the vicinity of the via holes for avoiding the planarized metal layer being torn around the via holes and thin enough not so as to produce caves when the sputtered metal layer is planarized by the pulsed laser beam.

Abstract: A method for fabricating a semiconductor device comprises forming a contact hole in an insulating film formed on a first wiring composed of an Al film, covering the insulating film with an Al film for a second wiring, applying laser beam pulses to the Al film for a second wiring from above, and patterning the Al film to form a second wiring.

Abstract: Fuse-type ROM are provided with fuses which are formed on an insulating film, connected to conductor lines, and covered by a protective film. In order to write information into the fuse-type ROMs a ramp voltage is applied to the fuses so as to selectively and electrically blow the fuses without breaking the protective film. The ramp voltage increases substantially linearly, to a peak value, at a rate of from 10.sup.3 to 10.sup.5 volts/sec.

Abstract: A method of creating a conducting link between conducting paths of semiconductor device at a specified portion in an integrated circuit. The link is formed using a polysilicon insulating layer having a metal film formed thereon. To activate the link, it is heated by a laser beam and the polysilicon insulating layer and metal film react to form a conducting layer of metal silicide that links the conducting paths. The activation is accomplished by a chemical reaction which forms the metal-silicide at an activation temperature less than an ion diffusion temperature. The lower activation temperature protects devices close to the heated spot, the surface of the substrate is not damaged by a high temperature and the reliablity of the device is increased.

Abstract: A metal silicide interconnection technique selectively forming a metal silicide layer on a silicon layer followed by heat treating the layers so that a surface silicon dioxide layer is formed and the metal silicide layer is forced down and is buried under the silicon dioxide layer. This silicon dioxide layer has an even top surface.

Abstract: A process for producing a single crystalline semiconductor island on an insulator, comprising the steps of providing a semiconductor island comprising a nonmonocrystalline semiconductor on an insulator; forming an energy-absorbing cap layer which coats at least the upper and side surfaces of the semiconductor island; irradiating the energy-absorbing cap layer with an energy beam; and melting and transforming the coated nonmonocrystalline semiconductor into a single crystalline semiconductor with the heat generated in the energy-absorbing cap layer.