Abstract: The present invention provides a test system for a semiconductor device, the test system comprising: a test data generator for generating test data, the test data generator being provided in an output section; a delay circuit for, in order to use as expected-value data the test data after the test data is transferred through inside a chip, adjusting a time difference between the test data and the expected-value data; a comparator for, against the expected-value data, comparing and verifying the test data after the test data is transferred outside the chip, the comparator being provided in an input section; and an external wiring for connecting an output pin connected to the test data generator and an input pin connected to the comparator.

Abstract: A test system includes a semiconductor device having a circuit configuration including an input buffer circuit, an output buffer circuit, and an internal logic, a random data generation circuit being provided at the front stage of the output buffer circuit; a random data generator, incorporating a random data generation circuit, for applying a random data to an input of the input buffer circuit from the random data generation circuit; and a test board on which the semiconductor device and random data generator is mounted and electrically connected to each other.

Abstract: The present invention provides a test system for a semiconductor device, the test system comprising: a test data generator for generating test data, the test data generator being provided in an output section; a delay circuit for, in order to use as expected-value data the test data after the test data is transferred through inside a chip, adjusting a time difference between the test data and the expected-value data; a comparator for, against the expected-value data, comparing and verifying the test data after the test data is transferred outside the chip, the comparator being provided in an input section; and an external wiring for connecting an output pin connected to the test data generator and an input pin connected to the comparator.

Abstract: A device under test (DUT) board for testing is electrically connected to a solder ball of a package. A contactor of the board is directly attached to the solder ball. Thus, there is little influence by bouncing of a power source and ground, even when an LSI under test is operated at high speed and low voltage, and malfunctions are rare.

Abstract: A test board for testing a semiconductor device. The semiconductor device includes at least first and second input terminals and an input/output buffer cell for buffering a signal obtained from the first input terminal to output an internal signal. The operation of the semiconductor device is controlled by a signal obtained from the second input terminal. The test board includes a first delay element for delaying a signal to be transmitted therethrough for a first signal propagation delay time and a second delay element for delaying a signal to be transmitted therethrough for a second signal propagation delay time different from the first signal propagation delay time.

Abstract: A clock CLK is applied to one input of an MUX 3, while data DATA1 is applied to a delay circuit 2 and to one input of a receiver 6. The delay circuit 2 delays the data DATA1 for a predetermined period of time, and outputs a delay data DDT to the other input of the MUX 3. A test-mode signal STM is applied to a control input of the MUX 3. The MUX 3 is then outputs either the clock CLK or the delay data DDT to respective control inputs of the receiver 6 and a drive 8 on the basis of the test-mode signal STM. The receiver 6 compares the data DATA1 and a reference voltage VREF, and performs buffering on the basis of its comparison result to output an internal signal. Thus, a semiconductor device and a test (DUT) board thereof can achieve a high-precision timing test, irrespective of the timing skew of a tester.

Abstract: Provided is a semiconductor device having an I/O buffer cell capable of performing a timing verification test of high accuracy. A phase comparator (2) compares the phase of data (DATA) and that of a clock (CLK) and outputs a phase comparison result to a first input of an MUX (3). A test mode signal (STM1) inputted from a test mode terminal (14) is provided to the control input of the MUX (3) through a test mode input section (4). The MUX (3) receives at its second input the output signal of an internal logic (50) through a signal input section (9) and, based on the test mode signal (STM1), outputs either the phase comparison result or the output signal of the internal logic (50), to the input section of a driver (8).

Abstract: A semiconductor test device capable of solving a problem of a conventional one in that in the resistance measurement of a semiconductor integrated circuit it was difficult for the measurement error due to contact resistance or wiring resistance to be limited within a desired amount. The present semiconductor test device includes, in a semiconductor integrated circuit having a first semiconductor switch functioning as a pullup resistor and a second semiconductor switch functioning as a pulldown resistor, a measuring circuit for bringing the first and second semiconductor switches into conduction at the same time in response to a signal fed from a control circuit, a voltage measuring circuit for measuring the voltage at a connecting point between the two semiconductor switches, and a current measuring circuit for measuring a through current flowing through the two semiconductor switches.

Abstract: A probe card which solves a problem involved in conventional probe cards in that the yield of the LSIs is reduced because non-defectives can be misjudged as defectives, which is due to failure of test signal application to LSIs owing to a contact failure between probe needles and bonding pads, which in turn due to the lack of needle pressure resulting from the lack of thickness of the probe needles in the conventional probe cards. The present probe card device includes units, each of which has a plurality of probe needles juxtaposed on a first insulating sheet, and separated by second insulating sheets with a thickness of about 10 .mu.m. The units are stacked in multilayer and fixed to a probe card substrate. The first insulating sheet has many grooves to which the second insulating sheets can be inserted.

Abstract: A semiconductor integrated device including a first circuit block, a second circuit block, a first supply interconnection connected to the first circuit block to supply power thereto, a second supply interconnection connecting the first supply interconnection to the second circuit block, and a switch inserted across the first and second supply interconnections. The switch has a structure equivalent to a plurality of switching elements disposed in parallel on a substrate. The switch is opened by a break command output from the first circuit block so that the second supply interconnection is disconnected from the first supply interconnection, thereby preventing a standby current from flowing to the second circuit block when it is unused. This can solve a problem of a conventional semiconductor integrated device in that the standby current flowing to the second circuit block wastes power even if the second block is not used.

Abstract: A method of testing a semiconductor device operating according to predetermined testing information. An output signal of the semiconductor device is received through a signal transmission line and a reference voltage is generated in accordance with an expected logical level of the output signal. The reference voltage is compared with a voltage of the output signal thus received and a current flow is supplied to the signal transmission line in accordance with the result. A logical level of the output signal thus received is determined and a decision is made whether the semiconductor device operates correctly.

Abstract: A semiconductor testing apparatus includes a comparator for receiving a signal output to a pin terminal of a semiconductor device under test through a transmission line and determining a logical level of the received signal. Semiconductor testing apparatus 1 further includes a current supply circuit for comparing a voltage of an input terminal of comparator with a reference voltage applied by reference voltage sources and supplying a current to transmission line. When a signal ringing on transmission line and a reflection with undershoot and overshoot at input terminal occur, current supply circuit supplies a current to transmission line in accordance with a relationship of magnitude between the voltage at input terminal and the reference voltage. The current supply to transmission line is made to inhibit the overshoot and undershoot of the signal. This allows comparator to carry out a functional testing and a measurement of DC/AC characteristics of a semiconductor device at precise timing and at high speed.

Abstract: A probing plate for wafer testing is provided with a plurality of probes arranged so as to correspond to a plurality of bonding pads of semiconductor devices fabricated on a semiconductor wafer. The probing plate has a base plate formed of an insulating material, such as a photosensitive glass, and has contact fingers each having a raised portion in the free end thereof, contact conductors respectively formed on the surfaces of the raised portions of the contact fingers so as to be brought into contact with the corresponding bonding pads, and wiring conductors formed in a predetermined pattern on the surface of the base plate so as to extend respectively from the contact conductors. The contact conductors and the wiring conductors are formed simultaneously by a photolithographic process. The contact fingers and the raised portions thereof are also formed by subjecting the base plate to a photolithographic process.