Abstract: A graphic search apparatus is disclosed. A storage part stores first trace information including information pertinent to graphic data. The first trace information is acquired by tracing sets of the graphic data included in a search range based on a sort result from sorting the sets of the graphic data included in the search range. One of multiple areas included in a predetermined area is set as the search range. A control part starts from beginning graphic data corresponding to the information included in the first trace information stored in the storage part, searches for the graphic data toward an adjacent search range to the search range including the beginning graphic data, and controls a process for updating the first trace information.

Abstract: A layout design support apparatus divides a first module obtained by dividing a semiconductor integrated circuit into a plurality of second modules in order to support a layout design for determining the disposition of each cell constituting the semiconductor integrated circuit and wiring, and makes the detailed design of a layout for determining the disposition of each cell in the second module and wiring for each second module.

Abstract: A layout design apparatus that designs a layout of a semiconductor integrated circuit having a plurality of layers, the apparatus includes an extractor configured to extract, when given a lower module used at multiple locations inside an upper module, information regarding upper layer wiring near respective placement locations where the lower module is placed, and a layout design unit configured to lay out the lower module by setting prohibited wiring regions in a layout database based on the upper layer wiring information extracted from multiple locations. The prohibited wiring regions are specific regions that prohibit wiring processes therein, and the layout database is data for laying out the lower module.

Abstract: A layout design support apparatus divides a first module obtained by dividing a semiconductor integrated circuit into a plurality of second modules in order to support a layout design for determining the disposition of each cell constituting the semiconductor integrated circuit and wiring, and makes the detailed design of a layout for determining the disposition of each cell in the second module and wiring for each second module.

Abstract: A design support apparatus is provided, including control portion executes layout program to implement a position judging section which performs position judgment to check, for every net, the net being formed by a first cell to be called ‘driver’ and one or a plurality of cells driven via an output terminal of the first cell to be called ‘receiver(s)’, whether or not said driver exists outside a predetermined region for enclosing said receiver(s), and a layout section which determines a base point from an inside of said predetermined region, with respect to said net where it is judged that said driver exists outside said predetermined region, and arranges said diagonal wiring for wiring which connects said output terminal of said driver with said base point when said base point can be connected with an input terminal of said receiver by means of vertical and/or horizontal wiring.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.

Abstract: A design support apparatus is provided, including control portion executes layout program to implement a position judging section which performs position judgment to check, for every net, the net being formed by a first cell to be called ‘driver’ and one or a plurality of cells driven via an output terminal of the first cell to be called ‘receiver(s)’, whether or not said driver exists outside a predetermined region for enclosing said receiver(s), and a layout section which determines a base point from an inside of said predetermined region, with respect to said net where it is judged that said driver exists outside said predetermined region, and arranges said diagonal wiring for wiring which connects said output terminal of said driver with said base point when said base point can be connected with an input terminal of said receiver by means of vertical and/or horizontal wiring.

Abstract: A design data processing method is a method of processing hierarchically configured design data, comprises the steps of: a) obtaining first design data of a predetermined rank of hierarchy; b) obtaining second design data of a rank of hierarchy higher than the predetermined rank of hierarchy; and c) combining the second design data to the first design data.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.

Abstract: When a logical block is built in an LSI logic design stage, a maximum delay value between pins of a block is set based on a designer's estimation, or information of a netlist after the netlist is generated. Pins can be grouped. A delay value in a connection between pins is represented by the largest value. Additionally, a plurality of internal memory elements within a logical block are represented by one or a plurality of internal latches. Also as a delay value between a pin and an internal latch, or between an internal latch and a pin, the largest value is selected from among a plurality of delay values, and set as a representative value.

Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out Thereby and afterwards executes the program.

Abstract: When a logical block is built in an LSI logic design stage, a maximum delay value between pins of a block is set based on a designer's estimation, or information of a netlist after the netlist is generated. Pins can be grouped. A delay value in a connection between pins is represented by the largest value. Additionally, a plurality of internal memory elements within a logical block are represented by one or a plurality of internal latches. Also as a delay value between a pin and an internal latch, or between an internal latch and a pin, the largest value is selected from among a plurality of delay values, and set as a representative value.

Abstract: The present invention provides a placement/net wiring processing system using an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring.

Abstract: A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Abstract: A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.