Abstract: An Insulated Gate Field Effect Transistor (IG FET) comprises two depletion mode gate portions formed along the surface of a V-shaped recess in a semiconductor layer, an enhancement mode gate portion disposed between the two depletion mode gate portions, and a source region and a drain region disposed on respective sides of, and adjacent to, the depletion mode gate portion at the surface of the semiconductor layer. The V-shaped recess extends downwardly from the surface of, and through, a first semiconductor layer having comparatively low impurity concentration into an underlying second semiconductor layer having comparatively high impurity concentration. The first semiconductor layer provides, in the recess, the depletion mode gate portion, and the second semiconductor layer provides, in the recess, the enhancement mode gate portion of the IG FET.

Abstract: A method of manufacturing SOS type semiconductor devices having small leakage current comprising the steps of forming a single crystal semiconductor film on an insulator single crystal substrate, selectively forming a film for masking against oxidation on the surface of the single crystal semiconductor film, and thermally oxidizing the single crystal semiconductor film, in a region which is not covered with the masking film, down to the surface of the insulating single crystal substrate in a water vapor atmosphere having a high pressure which is at least more than atmospheric pressure.