Abstract: An apex is extracted from a designed wiring layout. In start/end portion circular arc processing a circular arc is added to the apex-containing portion, and the layout data file is rewritten so that a portion, representing a region surrounded by circular arc and two lines, is added to the wiring line. In bend portion circular arc processing circular arcs are added to the respective apex-containing portions, and the layout data file is rewritten so that: a portion corresponding to a region surrounded by the circular arc and two lines is added to the apex-containing portion of the layout when the determined angle is less than 180 degrees; a portion corresponding to a region surrounded by the circular arc and two lines is removed from the apex-containing portion of the layout when the determined angle exceeds 180 degrees.

Abstract: In a circuit layout design method for designing an integrated circuit having signal lines synchronously propagating signals, delay correction cells having provisional values are inserted into the signal lines extending from respective output drivers to corresponding output pads for a set of signals to be synchronized in the designed original circuit. Based on the circuit data having the delay correction cells thus inserted, a layout is designed, based on which resistance values for those respective signal lines are calculated. The resistance value for the respective delay correction cells are corrected so as to equalize the resistance values for those signal lines, and the layout pattern is corrected based on the circuit data having the corrected delay correction cells.

Abstract: An apex is extracted from a designed wiring layout. In start/end portion circular arc processing a circular arc is added to the apex-containing portion, and the layout data file is rewritten so that a portion, representing a region surrounded by circular arc and two lines, is added to the wiring line. In bend portion circular arc processing circular arcs are added to the respective apex-containing portions, and the layout data file is rewritten so that: a portion corresponding to a region surrounded by the circular arc and two lines is added to the apex-containing portion of the layout when the determined angle is less than 180 degrees; a portion corresponding to a region surrounded by the circular arc and two lines is removed from the apex-containing portion of the layout when the determined angle exceeds 180 degrees.

Abstract: In an area extracting step, areas interposed among tower post rows adjacent to one another, and rectangular areas interposed among the tower post rows and pads at outer peripheral portions of a chip are respectively extracted as areas in which equalization of wire spacings is performed. Areas interposed among tower post columns adjacent to one another, and rectangular areas interposed among the tower post columns and pads at outer peripheral portions of the chip are also respectively extracted as areas in which equalization of wire spacings is performed.

Abstract: A positioning region of external terminals is divided into a plurality of positioning sections, and at least one side or perimeter of a chip is assigned to each positioning section. The external terminals in each positioning section are allocated to the perimeter to which the positioning section is assigned. The external terminals allocated to each perimeter are grouped into groups arranged perpendicularly to the perimeter, and pads of the chip are also grouped. The external terminals of the groups are assigned to the pads of the corresponding groups. The external terminals and the pads assigned to each other are connected by linear virtual wirings. Further, it is checked whether the virtual wirings cross each other. If there are crossing virtual wirings, the correspondences between the external terminals and the pads are replaced with each other.

Abstract: A method includes: obtaining process technology definition data related to a process technology of each layer forming a basic cell, from a process technology definition file defining process technology definition data related to a process technology for use in fabricating a semiconductor integrated circuit, thereby holding a process technology definition table; obtaining device structure data including data related to a device template which defines a structure of each layer of the basic cell and data related to the structure of the layer defined in accordance with the device template, from a device structure definition file, thereby holding the obtained device structure data as a device structure definition table; and determining the structure of each layer defined in accordance with the device template held as the obtained device structure data, thereby generating the layout pattern of the basic cell forming the semiconductor integrated circuit.

Abstract: In an area extracting step, areas interposed among tower post rows adjacent to one another, and rectangular areas interposed among the tower post rows and pads at outer peripheral portions of a chip are respectively extracted as areas in which equalization of wire spacings is performed. Areas interposed among tower post columns adjacent to one another, and rectangular areas interposed among the tower post columns and pads at outer peripheral portions of the chip are also respectively extracted as areas in which equalization of wire spacings is performed.

Abstract: A positioning region of external terminals is divided into a plurality of positioning sections, and at least one of perimeters is assigned to each positioning section. The external terminals in each positioning section are allocated to the perimeter to which the positioning section is assigned. The external terminals allocated to each perimeter are grouped into groups arranged perpendicularly to the perimeter, and the pads arranged are also grouped. The external terminals of the groups are assigned to the pads of the corresponding groups. The external terminals and the pads assigned to each other are connected by linear virtual wirings. Further, it is checked whether the virtual wirings cross each other. If there are crossing virtual wirings, the correspondences between the external terminals and the pads are replaced with each other.

Abstract: A method includes: obtaining process technology definition data related to a process technology of each layer forming the basic cell, from a process technology definition file defining process technology definition data related to a process technology for use in fabricating a semiconductor integrated circuit, thereby holding a process technology definition table; obtaining device structure data including data related to a device template which defines a structure of each layer of the basic cell and data related to the structure of the layer defined in accordance with the device template, from a device structure definition file, thereby holding the obtained device structure data as a device structure definition table; and determining the structure of each layer defined in accordance with the device template held as the obtained device structure data, thereby generating the layout pattern of the basic cell forming the semiconductor integrated circuit.

Abstract: Disclosed is a method for microwave plasma processing characterized by providing a plasma processing period of time having no radio-frequency voltage applied to the sample stage. Particularly, if the present invention is used for the shaping by etching of the conductive material layer provided on an underlying insulation material, effects such as shortening of processing time and improvement of etching accuracy can be obtained in the case that the radio-frequency voltage is applied only for the period of time for removing the surface oxide film of the portion to be etched, or in the case that the radio-frequency voltage is further applied until nearly the time to initiate over-etching, and, the latter case is also effective for making the side wall of the portion to be etched vertical.