Patents by Inventor Ryoji Ikegaya

Ryoji Ikegaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180159557
    Abstract: The present technology relates to a coding device and a coding method that makes it possible to correspond to a DVB-Like LDPC code and an LDPC code in an ETRI format. A coding device includes: a first LDPC coding unit configured to generate an LDPC code of a predetermined information word by using a first parity check matrix; a first parity interleaving unit configured to interleave a parity bit of the LDPC code; and a second LDPC coding unit configured to generate an LDPC code in an ETRI format by using a second parity check matrix with respect to the LDPC code in which the parity bit is interleaved. The present technology can be applied, for example, to a coding device or the like.
    Type: Application
    Filed: May 6, 2016
    Publication date: June 7, 2018
    Inventors: YUJI SHINOHARA, MAKIKO YAMAMOTO, RYOJI IKEGAYA
  • Patent number: 9906327
    Abstract: The present disclosure relates to a receiving device, a receiving method, and a program that can reduce power consumption. A Viterbi decoding unit performs Viterbi decoding on a likelihood as a processing target, a byte de-interleaver delays a part of a decoding result of Viterbi decoding, and an RS decoding unit performs RS decoding on the decoding result after delaying by the byte de-interleaver. A likelihood converting unit controls decoding of the likelihood to improve reliability of the decoding result. Then, when all of a predetermined number of decoding results by the RS decoding unit are succeeded or failed, the decode stop determination unit determines to stop subsequent decoding on the likelihood as a processing target. The present technology may be applied to, for example, a receiving device that receives digital terrestrial broadcasting compatible with the ISDB-T standard, or the like.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 27, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Ryoji Ikegaya, Takashi Yokokawa
  • Patent number: 9886399
    Abstract: Data are stored using a writing method according to the property of the data in a storage device. An area defining unit defines, in a second memory, a system area for storing system information causing a system to operate and a cache area temporarily storing data of a first memory. A moving processing unit moves data stored in the cache area to the first memory at a predetermined point in time. An access control unit accesses the second memory in accordance with the definition with regard to access corresponding to the system area or the cache area, and read data from the first memory with regard to read-access corresponding to those other than the system area and the cache area.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: February 6, 2018
    Assignee: Sony Corporation
    Inventors: Ken Ishii, Keiichi Tsutsui, Ryoji Ikegaya
  • Patent number: 9887807
    Abstract: A transmitter transmits data using Orthogonal Frequency Division, OFDM, symbols. The transmitter comprising a forward error correction encoder configured to encode the data to form forward error correction encoded frames of encoded data cells, a service frame builder configured to form a service frame for transmission comprising a plurality of forward error correction encoded frames, a convolutional interleaver comprising a plurality of delay portions and configured to convolutionally interleave the data cells of the service frames, a modulation symbol mapper configured to map the interleaved and encoded data cells of the service frames onto modulation cells, and a modulator configured to modulate the sub-carriers of one or more OFDM symbols with the modulation cells.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: February 6, 2018
    Assignee: Sony Corporation
    Inventors: Nabil Sven Loghin, Ryoji Ikegaya
  • Patent number: 9852812
    Abstract: There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 26, 2017
    Assignee: Sony Corporation
    Inventors: Hiroyuki Iwaki, Ken Ishii, Ryoji Ikegaya, Kenichi Nakanishi, Yasushi Fujinami, Naohiro Adachi
  • Publication number: 20170185478
    Abstract: The convenience of an information processing system is improved. In a memory controller of the information processing system, a request generation unit generates, with respect to a nonvolatile memory including a data area in which data is stored and a redundancy area in which a redundancy for performing error detection and error correction of the data is stored, a request of requesting writing or reading for any one of the data, and the redundancy, a code word constituted of the data and the redundancy. A control unit issues the generated request and controls writing and reading with respect to the nonvolatile memory.
    Type: Application
    Filed: June 23, 2015
    Publication date: June 29, 2017
    Applicant: SONY CORPORATION
    Inventors: LUI SAKAI, KEIICHI TSUTSUI, YASUSHI FUJINAMI, HIROYUKI IWAKI, KEN ISHII, NAOHIRO ADACHI, RYOJI IKEGAYA, KENICHI NAKANISHI
  • Publication number: 20170187393
    Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 7/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
    Type: Application
    Filed: February 5, 2015
    Publication date: June 29, 2017
    Applicant: SONY CORPORATION
    Inventors: Ryoji IKEGAYA, Makiko YAMAMOTO, Yuji SHINOHARA
  • Publication number: 20170187392
    Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
    Type: Application
    Filed: February 5, 2015
    Publication date: June 29, 2017
    Applicant: SONY CORPORATION
    Inventors: Ryoji IKEGAYA, Makiko YAMAMOTO, Yuji SHINOHARA
  • Publication number: 20170170846
    Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
    Type: Application
    Filed: February 5, 2015
    Publication date: June 15, 2017
    Applicant: SONY CORPORATION
    Inventors: Ryoji IKEGAYA, Makiko YAMAMOTO, Yuji SHINOHARA
  • Publication number: 20170160952
    Abstract: A latency time of memory access is suppressed. A memory controller includes memory control units and a connection switching unit. The memory control units each independently generate a request to a memory on the basis of a command from a computer. Any one of the memory control units and the memory are connected in response to a connection request from each of the memory control units, and the request is output to the memory. A memory system is constituted of the memory and the memory controller. An information processing system is constituted of the memory system and the computer.
    Type: Application
    Filed: June 9, 2015
    Publication date: June 8, 2017
    Inventors: KENICHI NAKANISHI, HIROYUKI IWAKI, KEN ISHII, RYOJI IKEGAYA, KENTAROU MORI
  • Publication number: 20170147433
    Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.
    Type: Application
    Filed: May 20, 2015
    Publication date: May 25, 2017
    Inventors: TATSUO SHINBASHI, LUI SAKAI, RYOJI IKEGAYA
  • Publication number: 20170141877
    Abstract: The present disclosure relates to a receiving device, a receiving method, and a program that can reduce power consumption. A Viterbi decoding unit performs Viterbi decoding on a likelihood as a processing target, a byte de-interleaver delays a part of a decoding result of Viterbi decoding, and an RS decoding unit performs RS decoding on the decoding result after delaying by the byte de-interleaver. A likelihood converting unit controls decoding of the likelihood to improve reliability of the decoding result. Then, when all of a predetermined number of decoding results by the RS decoding unit are succeeded or failed, the decode stop determination unit determines to stop subsequent decoding on the likelihood as a processing target. The present technology may be applied to, for example, a receiving device that receives digital terrestrial broadcasting compatible with the ISDB-T standard, or the like.
    Type: Application
    Filed: June 23, 2015
    Publication date: May 18, 2017
    Inventors: Ryoji Ikegaya, Takashi Yokokawa
  • Publication number: 20170109099
    Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.
    Type: Application
    Filed: May 19, 2015
    Publication date: April 20, 2017
    Inventors: HIROYUKI IWAKI, KEN ISHII, RYOJI IKEGAYA, KENICHI NAKANISHI, YASUSHI FUJINAMI, NAOHIRO ADACHI
  • Patent number: 9621191
    Abstract: In group-wise interleaving, interleaving of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15 is performed in a unit of a bit group of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code that has undergone group-wise interleaving is returned to an original arrangement. The technology can be applied to a case of transmitting data using the LDPC code. The data processing device and data processing method can ensure excellent communication quality in data transmission using an LDPC code.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 11, 2017
    Assignee: SONY CORPORATION
    Inventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara
  • Publication number: 20170093435
    Abstract: The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.
    Type: Application
    Filed: March 6, 2015
    Publication date: March 30, 2017
    Applicant: SONY CORPORATION
    Inventors: Ryoji IKEGAYA, Makiko YAMAMOTO, Yuji SHINOHARA
  • Publication number: 20170093430
    Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
    Type: Application
    Filed: May 8, 2015
    Publication date: March 30, 2017
    Applicant: SONY CORPORATION
    Inventors: Ryoji IKEGAYA, Makiko YAMAMOTO, Yuji SHINOHARA
  • Patent number: 9608668
    Abstract: Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if a determination-target symbol has an error or not, and detecting an error position, the error position being a position of the symbol having an error; changing, by a determination-target changing unit, the position of the determination-target symbol of the received word every time the determination process is executed; detecting, by an undetected-position detector, if the predetermined condition is satisfied, the error position of the symbol, for which the determination process is not executed, based on a relation between the error position and a variable generated from the received word; and correcting, by an error corrector, an error at the error position detected by the error-position detector and the undetected-position detector.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 28, 2017
    Assignee: Sony Corporation
    Inventors: Ryoji Ikegaya, Tatsuo Shinbashi, Yasushi Fujinami
  • Publication number: 20170063494
    Abstract: A transmitter transmits data using Orthogonal Frequency Division, OFDM, symbols. The transmitter comprising a forward error correction encoder configured to encode the data to form forward error correction encoded frames of encoded data cells, a service frame builder configured to form a service frame for transmission comprising a plurality of forward error correction encoded frames, a convolutional interleaver comprising a plurality of delay portions and configured to convolutionally interleave the data cells of the service frames, a modulation symbol mapper configured to map the interleaved and encoded data cells of the service frames onto modulation cells, and a modulator configured to modulate the sub-carriers of one or more OFDM symbols with the modulation cells.
    Type: Application
    Filed: November 10, 2016
    Publication date: March 2, 2017
    Applicant: Sony Corporation
    Inventors: Nabil Sven LOGHIN, Ryoji IKEGAYA
  • Publication number: 20160373135
    Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15, 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
    Type: Application
    Filed: February 24, 2015
    Publication date: December 22, 2016
    Applicant: SONY CORPORATION
    Inventors: Ryoji IKEGAYA, Makiko YAMAMOTO, Yuji SHINOHARA
  • Publication number: 20160365877
    Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
    Type: Application
    Filed: February 5, 2015
    Publication date: December 15, 2016
    Applicant: SONY CORPORATION
    Inventors: Ryoji IKEGAYA, Makiko YAMAMOTO, Yuji SHINOHARA